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Freescale Semiconductor, Inc.
HC05JB4GRS/H REV 2
68HC05JB4 68HC705JB4
Freescale Semiconductor, Inc...
SPECIFICATION (General Release)
February 24, 1999
Semiconductor Products Sector
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
(c) Motorola, Inc., 1999
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Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS Section SECTION 1 GENERAL DESCRIPTION 1.1 1.2 1.3 1.4 1.4.1 1.4.2 1.4.3 1.4.4 1.4.5 1.4.6 1.4.7 1.4.8 1.4.9 FEATURES ...................................................................................................... 1-1 MASK OPTIONS.............................................................................................. 1-2 MCU STRUCTURE.......................................................................................... 1-2 FUNCTIONAL PIN DESCRIPTION.................................................................. 1-4 VDD AND VSS .............................................................................................. 1-4 OSC1, OSC2 ............................................................................................... 1-4 RESET......................................................................................................... 1-6 IRQ (MASKABLE INTERRUPT REQUEST)................................................ 1-6 V3.3 ............................................................................................................. 1-6 D+ and D- ................................................................................................... 1-6 PA0-PA7 ...................................................................................................... 1-6 PB0-PB4 ...................................................................................................... 1-7 PC0-PC5...................................................................................................... 1-7 SECTION 2 MEMORY 2.1 2.2 2.3 2.4 I/O AND CONTROL REGISTERS ................................................................... 2-2 RAM ................................................................................................................. 2-2 ROM................................................................................................................. 2-2 I/O REGISTERS SUMMARY ........................................................................... 2-3 SECTION 3 CENTRAL PROCESSING UNIT 3.1 3.2 3.3 3.4 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 REGISTERS .................................................................................................... 3-1 ACCUMULATOR (A)........................................................................................ 3-2 INDEX REGISTER (X) ..................................................................................... 3-2 STACK POINTER (SP) .................................................................................... 3-2 PROGRAM COUNTER (PC) ........................................................................... 3-2 CONDITION CODE REGISTER (CCR) ........................................................... 3-3 Half Carry Bit (H-Bit) .................................................................................... 3-3 Interrupt Mask (I-Bit) .................................................................................... 3-3 Negative Bit (N-Bit) ...................................................................................... 3-3 Zero Bit (Z-Bit) ............................................................................................. 3-3 Carry/Borrow Bit (C-Bit) ............................................................................... 3-4 SECTION 4 INTERRUPTS 4.1 4.2 4.3 4.4 INTERRUPT VECTORS .................................................................................. 4-1 INTERRUPT PROCESSING............................................................................ 4-2 RESET INTERRUPT SEQUENCE .................................................................. 4-4 SOFTWARE INTERRUPT (SWI) ..................................................................... 4-4
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MC68HC05JB4 REV 2
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GENERAL RELEASE SPECIFICATION February 24, 1999
TABLE OF CONTENTS Section Page
4.5 HARDWARE INTERRUPTS ............................................................................ 4-4 4.5.1 External Interrupt IRQ.................................................................................. 4-4 4.5.2 External Interrupt IRQ2................................................................................ 4-5 4.5.3 IRQ Control/Status Register (ICSR) - $0A................................................... 4-6 4.5.4 Port A External Interrupts (PA0-PA3, by mask option) ................................ 4-7 4.5.5 Timer1 Interrupt (TIMER1)........................................................................... 4-8 4.5.6 USB Interrupt (USB) .................................................................................... 4-8 4.5.7 MFT Interrupt (MFT) .................................................................................... 4-8
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SECTION 5 RESETS 5.1 POWER-ON RESET ........................................................................................ 5-2 5.2 EXTERNAL RESET ......................................................................................... 5-2 5.3 INTERNAL RESETS ........................................................................................ 5-2 5.3.1 Power-On Reset (POR) ............................................................................... 5-2 5.3.2 USB Reset ................................................................................................... 5-3 5.3.3 Computer Operating Properly (COP) Reset ................................................ 5-3 5.3.4 Low Voltage Reset (LVR) ............................................................................ 5-3 5.3.5 Illegal Address Reset................................................................................... 5-4 SECTION 6 LOW POWER MODES 6.1 6.2 6.3 STOP MODE.................................................................................................... 6-3 WAIT MODE .................................................................................................... 6-3 DATA-RETENTION MODE.............................................................................. 6-3 SECTION 7 INPUT/OUTPUT PORTS 7.1 7.2 7.2.1 7.2.2 7.2.3 7.3 7.3.1 7.3.2 7.3.3 7.4 7.4.1 7.4.2 SLOW FALLING-EDGE OUTPUT DRIVER..................................................... 7-1 PORT-A............................................................................................................ 7-2 Port-A Data Register.................................................................................... 7-2 Port-A Data Direction Register .................................................................... 7-3 Port-A Pull-up Control Register ................................................................... 7-3 PORT-B............................................................................................................ 7-3 Port-B Data Register.................................................................................... 7-4 Port-B Data Direction Register .................................................................... 7-4 Port-B Pull-up Control Register ................................................................... 7-4 PORT-C ........................................................................................................... 7-4 Port-C Data Register ................................................................................... 7-5 Port-C Data Direction Register .................................................................... 7-5
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MC68HC05JB4 REV 2
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February 24, 1999 GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS Section SECTION 8 MULTI-FUNCTION TIMER 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.5 OVERVIEW...................................................................................................... 8-2 COMPUTER OPERATING PROPERLY (COP) WATCHDOG ........................ 8-2 MFT REGISTERS ............................................................................................ 8-3 Timer Counter Register (TCNT) $09 ........................................................... 8-3 Timer Control/Status Register (TCSR) $08 ................................................. 8-3 OPERATION DURING STOP MODE .............................................................. 8-4 COP CONSIDERATION DURING STOP MODE............................................. 8-4 SECTION 9 16-BIT TIMER 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 TIMER REGISTERS (TMRH, TMRL)............................................................... 9-2 ALTERNATE COUNTER REGISTERS (ACRH, ACRL) .................................. 9-4 INPUT CAPTURE REGISTERS ...................................................................... 9-5 OUTPUT COMPARE REGISTERS ................................................................. 9-6 TIMER CONTROL REGISTER (TCR) ............................................................. 9-8 TIMER STATUS REGISTER (TSR)................................................................. 9-9 TIMER OPERATION DURING WAIT MODE................................................. 9-10 TIMER OPERATION DURING STOP MODE ................................................ 9-10 SECTION 10 UNIVERSAL SERIAL BUS MODULE 10.1 FEATURES .................................................................................................... 10-1 10.2 OVERVIEW.................................................................................................... 10-2 10.2.1 USB Protocol ............................................................................................. 10-2 10.2.2 Reset Signaling.......................................................................................... 10-8 10.2.3 Suspend..................................................................................................... 10-9 10.2.4 Resume After Suspend.............................................................................. 10-9 10.2.5 Low Speed Device................................................................................... 10-10 10.3 CLOCK REQUIREMENTS........................................................................... 10-10 10.4 HARDWARE DESCRIPTION....................................................................... 10-10 10.4.1 Voltage Regulator .................................................................................... 10-11 10.4.2 USB Transceiver...................................................................................... 10-11 10.4.3 Receiver Characteristics.......................................................................... 10-12 10.4.4 USB Control Logic ................................................................................... 10-14 10.5 I/O REGISTER DESCRIPTION ................................................................... 10-17 10.5.1 USB Address Register (UADDR)............................................................. 10-18 10.5.2 USB Interrupt Register 0 (UIR0) .............................................................. 10-19 10.5.3 USB Interrupt Register 1 (UIR1) .............................................................. 10-20 10.5.4 USB Control Register 0 (UCR0) .............................................................. 10-21 10.5.5 USB Control Register 1 (UCR1) .............................................................. 10-22 10.5.6 USB Control Register 2 (UCR2) .............................................................. 10-23
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GENERAL RELEASE SPECIFICATION February 24, 1999
TABLE OF CONTENTS Section Page
10.5.7 USB Status Register (USR)..................................................................... 10-25 10.5.8 USB Endpoint 0 Data Registers (UE0D0-UE0D7)................................... 10-25 10.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7) ................ 10-26 10.6 USB INTERRUPTS...................................................................................... 10-26 10.6.1 USB End of Transaction Interrupt............................................................ 10-26 10.6.2 Resume Interrupt ..................................................................................... 10-27 10.6.3 End of Packet Interrupt ............................................................................ 10-27 SECTION 11 ANALOG TO DIGITAL CONVERTER 11.1 11.2 11.3 11.4 ADC OPERATION ......................................................................................... 11-2 ADC STATUS AND CONTROL REGISTER (ADSCR).................................. 11-3 ADC DATA REGISTER (ADDR) .................................................................... 11-4 ADC DURING LOW POWER MODES .......................................................... 11-5 SECTION 12 INSTRUCTION SET 12.1 ADDRESSING MODES ................................................................................. 12-1 12.1.1 Inherent...................................................................................................... 12-1 12.1.2 Immediate .................................................................................................. 12-1 12.1.3 Direct ......................................................................................................... 12-2 12.1.4 Extended.................................................................................................... 12-2 12.1.5 Indexed, No Offset..................................................................................... 12-2 12.1.6 Indexed, 8-Bit Offset .................................................................................. 12-2 12.1.7 Indexed, 16-Bit Offset ................................................................................ 12-3 12.1.8 Relative...................................................................................................... 12-3 12.1.9 Instruction Types ....................................................................................... 12-3 12.1.10 Register/Memory Instructions .................................................................... 12-4 12.1.11 Read-Modify-Write Instructions ................................................................. 12-5 12.1.12 Jump/Branch Instructions .......................................................................... 12-5 12.1.13 Bit Manipulation Instructions...................................................................... 12-7 12.1.14 Control Instructions.................................................................................... 12-7 12.1.15 Instruction Set Summary ........................................................................... 12-8 SECTION 13 ELECTRICAL SPECIFICATIONS 13.1 13.2 13.3 13.4 13.5 13.6 MAXIMUM RATINGS..................................................................................... 13-1 THERMAL CHARACTERISTICS ................................................................... 13-1 DC ELECTRICAL CHARACTERISTICS........................................................ 13-2 USB DC ELECTRICAL CHARACTERISTICS ............................................... 13-3 USB LOW SPEED SOURCE ELECTRICAL CHARACTERISTICS............... 13-4 CONTROL TIMING ........................................................................................ 13-5
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MC68HC05JB4 REV 2
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February 24, 1999 GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS Section SECTION 14 MECHANICAL SPECIFICATIONS 14.1 14.2 28-PIN PDIP (CASE 710) .............................................................................. 14-1 28-PIN SOIC (CASE 751F)............................................................................ 14-1 APPENDIX A MC68HC705JB4 A.1 A.2 A.3 A.4 A.5 A.5.1 A.5.2 A.6 INTRODUCTION..............................................................................................A-1 MEMORY .........................................................................................................A-1 MASK OPTION REGISTER (MOR) .................................................................A-1 BOOTSTRAP MODE .......................................................................................A-2 EPROM PROGRAMMING ...............................................................................A-3 EPROM Program Control Register (PCR)...................................................A-3 Programming Sequence ..............................................................................A-3 EPROM PROGRAMMING SPECIFICATIONS ................................................A-5 Page
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GENERAL RELEASE SPECIFICATION February 24, 1999
TABLE OF CONTENTS Section Page
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MC68HC05JB4 REV 2
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February 24, 1999 GENERAL RELEASE SPECIFICATION
LIST OF FIGURES Figure 1-1 1-2 1-3 2-1 2-2 2-3 2-4 2-5 2-6 3-1 4-1 4-2 4-3 4-4 4-5 5-1 5-2 6-1 7-1 8-1 8-2 8-3 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 Title Page
MC68HC05JB4 Block Diagram........................................................................ 1-3 MC68HC05JB4 Pin Assignment ...................................................................... 1-4 Oscillator Connections ..................................................................................... 1-5 MC68HC05JB4 Memory Map .......................................................................... 2-1 MC68HC05JB4 I/O Registers $0000-$000F.................................................... 2-3 MC68HC05JB4 I/O Registers $0010-$001F.................................................... 2-4 MC68HC05JB4 I/O Registers $0020-$002F.................................................... 2-5 MC68HC05JB4 I/O Registers $0030-$003F.................................................... 2-6 COP Register (COPR) ..................................................................................... 2-6 MC68HC05 Programming Model ..................................................................... 3-1 Interrupt Stacking Order................................................................................... 4-2 Interrupt Flowchart ........................................................................................... 4-3 External Interrupt (IRQ) Logic .......................................................................... 4-5 External Interrupt (IRQ2) Logic ........................................................................ 4-6 IRQ Control and Status Register (ICSR)......................................................... 4-6 Reset Sources.................................................................................................. 5-1 COP Watchdog Register (COPR) ................................................................... 5-3 STOP and WAIT Flowchart.............................................................................. 6-2 Slow Falling-edge Output Driver ...................................................................... 7-1 Multi-Function Timer Block Diagram ................................................................ 8-1 Timer Counter Register.................................................................................... 8-3 Timer Control/Status Register (TCSR)............................................................. 8-3 Programmable Timer Block Diagram ............................................................... 9-1 Programmable Timer Counter Block Diagram ................................................. 9-2 Programmable Timer Counter Registers (TMRH, TMRL)................................ 9-3 Alternate Counter Block Diagram..................................................................... 9-4 Alternate Counter Registers (ACRH, ACRL).................................................... 9-4 Timer Input Capture Block Diagram................................................................. 9-5 Input Capture Registers (ICRH, ICRL)............................................................. 9-6 Timer Output Compare Block Diagram ............................................................ 9-7 Output Compare Registers (OCRH, OCRL) .................................................... 9-7 Timer Control Register (TCR) .......................................................................... 9-8 Timer Status Registers (TSR) .......................................................................... 9-9 USB Block Diagram ....................................................................................... 10-2 Supported Transaction Types per Endpoint................................................... 10-3 Supported USB Packet Types ....................................................................... 10-4 Sync Pattern................................................................................................... 10-4 SOP, Sync Signaling and Voltage Levels ...................................................... 10-5 CRC Block Diagram for Address and Endpoint Fields................................... 10-6 CRC Block Diagram for Data Packets ........................................................... 10-7 EOP Transaction Voltage Levels ................................................................... 10-8 EOP Width Timing.......................................................................................... 10-8 External Low Speed Device Configuration................................................... 10-10
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MC68HC05JB4 REV 2
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GENERAL RELEASE SPECIFICATION February 24, 1999
LIST OF FIGURES Figure 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 10-27 10-28 10-29 10-30 10-31 10-32 11-1 11-2 11-3 A-1 A-2 Title Page
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Regulator Electrical Connections ................................................................. 10-11 Low Speed Driver Signal Waveforms .......................................................... 10-12 Differential Input Sensitivity Over Entire Common Mode Range ................. 10-13 Data Jitter..................................................................................................... 10-14 Data Signal Rise and Fall Time.................................................................... 10-14 NRZI Data Encoding .................................................................................... 10-15 Flow Diagram for NRZI ................................................................................ 10-15 Bit Stuffing.................................................................................................... 10-16 Flow Diagram for Bit Stuffing ....................................................................... 10-17 USB Address Register (UADDR) ................................................................. 10-18 USB Interrupt Register 0 (UIR0) .................................................................. 10-19 USB Interrupt Register 1(UIR1) ................................................................... 10-20 USB Control Register 0 (UCR0)................................................................... 10-21 USB Control Register 1 (UCR1)................................................................... 10-22 USB Control Register 2 (UCR2)................................................................... 10-23 USB Status Register (USR) ......................................................................... 10-25 USB Endpoint 0 Data Register (UE0D0-UE0D7)......................................... 10-25 USB Endpoint 1/Endpoint2 Data Registers (UE1D0-UE1D7)...................... 10-26 OUT Token Data Flow for Receive Endpoint 0 ............................................ 10-28 SETUP Token Data Flow for Receive Endpoint 0........................................ 10-29 IN Token Data Flow for Transmit Endpoint 0 ............................................... 10-30 IN Token Data Flow for Transmit Endpoint 1/2 ............................................ 10-31 ADC Converter Block Diagram ...................................................................... 11-1 A/D Status and Control Register .................................................................... 11-3 A/D Data Register .......................................................................................... 11-4 MC68HC705JB4 Memory Map ........................................................................A-2 EPROM Programming Sequence ....................................................................A-4
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MC68HC05JB4 REV 2
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February 24, 1999 GENERAL RELEASE SPECIFICATION
LIST OF TABLES Table Title Page
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4-1 Reset/Interrupt Vector Addresses .................................................................... 4-1 8-1 RTI and COP Rates at fOP =3.0MHz................................................................ 8-2 10-1 Supported Packet Identifiers .......................................................................... 10-5 10-2 Register Summary ....................................................................................... 10-17 11-1 A/D Channel Assignments ............................................................................. 11-4 12-1 Register/Memory Instructions ........................................................................ 12-4 12-2 Read-Modify-Write Instructions...................................................................... 12-5 12-3 Jump and Branch Instructions........................................................................ 12-6 12-4 Bit Manipulation Instructions .......................................................................... 12-7 12-5 Control Instructions ........................................................................................ 12-7 12-6 Instruction Set Summary............................................................................... 12-8 12-7 Opcode Map................................................................................................. 12-14 13-1 DC Electrical Characteristics.......................................................................... 13-2 13-2 USB DC Electrical Characteristics ................................................................. 13-3 13-3 USB Low Speed Source Electrical Characteristics ........................................ 13-4 13-4 Control Timing................................................................................................ 13-5 A-1 EPROM Programming Electrical Characteristics .............................................A-5
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LIST OF TABLES Table Title Page
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MC68HC05JB4 REV 2
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February 24, 1999 GENERAL RELEASE SPECIFICATION
SECTION 1 GENERAL DESCRIPTION
The MC68HC05JB4 is a member of the low-cost, high-performance M68HC05 Family of 8-bit microcontroller units (MCUs). The M68HC05 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the popular M68HC05 central processing unit (CPU) and are available with a variety of subsystems, memory sizes and types, and package types. The MC68HC05JB4 is specifically designed to be used in applications where a low speed (1.5Mbps) Universal Serial Bus (USB) interface is required. 1.1 FEATURES * * * * * Industry standard M68HC05 CPU core Memory-mapped input/output (I/O) registers 3584 Bytes of user ROM 176 Bytes of user RAM (includes 64 byte stack) 19 Bidirectional I/O pins with the following added features: - PA[0:7]: - PA[0:3]: - - - - PA4: - PA[5:7]: - PA[6:7]: - - PB[0:4]: - - PB[0]: - PB[3:4]: - PC[0:3]:
MC68HC05JB4 REV 2
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Software enable Internal pull-up resistor (50k typical) Built-in schmitt triggered input level Maskable as extra input sources for IRQ interrupt Maskable Negative-Edge Only or Negative-Edge and Low-Level Interrupt Capability IRQ2 with built-in schmitt triggered input 10mA Sink output drive Maskable 10mA/25mA sink output drive Software enable Slow Edge Pull Down Devices Software enable Internal pull-up resistor (50k typical) Software enable Slow Edge Pull Down Devices ICAP1 with built-in schmitt triggered input AD[4:5] AD[0:3]
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GENERAL RELEASE SPECIFICATION February 24, 1999
*
Fully compliant to Low Speed USB with 3 Endpoints: - 1 Control Endpoint (2x8 byte buffer) - 2 Interrupt Endpoints (1x8 byte buffer shared)
* * * * * * * * * * 1.2
6-channel 8-bit Analog-to-Digital Converter (ADC) Multi-function Timer (MFT) 16-bit Timer with 1 input capture and 1 output compare Low Voltage Reset (LVR) Circuit Computer Operating Properly (COP) Watchdog Reset Provide a 3.3V 10% DC Voltage for USB pull-up resistor Fully Static Operation with no Minimum Clock Speed Illegal Address Reset Power-Saving STOP and WAIT Modes Available in 28-Pin PDIP and 28-Pin SOIC packages
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MASK OPTIONS
The following mask options are available: * * * * * * 1.3 Enable PA0 to PA3 as extra IRQ interrupt sources. External interrupt pins (IRQ, PA0 to PA3): negative edge-triggered or negative edge- and low level-triggered. High current (25mA) output on PA6 and PA7. OSC: crystal/ceramic resonator start up delay, 4064 or 128 clock cycles. LVR: enabled or disabled. COP: enabled or disabled.
MCU STRUCTURE Figure 1-1 shows the structure of MC68HC05JB4 MCU.
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MC68HC05JB4 REV 2
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February 24, 1999 GENERAL RELEASE SPECIFICATION
PA0 PA1 PA2 PORT A PA3 PA4/IRQ2 PA5 PA6 PA7
DATA DIRECTION REG. A
VDD CPU CONTROL 68HC05 CPU RESET and IRQ ALU LVR VREF POWER SUPPLY VSS V3.3
RESET IRQ
ACCUM CPU REGISINDEX REG Core TImer 0 0 0 0 0 0 0 0 1 1 STK PNTR
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PB0/ICAP1 PB1 PB2 PB3/AD4 PB4/AD5 PORT B
DATA DIRECTION REG. B
OSC /2
OSC 1 OSC 2
PROGRAM COUNTER
16-bit Timer
(ICAP1)
shared with PB0
COND CODE REG 1 1 1 H I N Z C Low Speed USB D+ D-
PC0/AD0 PC1/AD1 PC2/AD2 PC3/AD3 PC4/VRH PC5/VRL PORT C
DATA DIRECTION REG. C
176 Bytes RAM 8-bit ADC
3584 bytes ROM
Figure 1-1. MC68HC05JB4 Block Diagram
MC68HC05JB4 REV 2
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GENERAL RELEASE SPECIFICATION February 24, 1999
PC2/AD2 PC1/AD1 PC0/AD0 PB4/AD5 PB3/AD4 PB2 PB1 PB0/ICAP1 RESET IRQ
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PC3/AD3 PC4/VRH PC5/VRL 3.3V D+ D- VDD OSC1 OSC2 VSS PA7 PA6 PA5 PA4/IRQ2
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PA0 PA1 PA2 PA3
Figure 1-2. MC68HC05JB4 Pin Assignment 1.4 FUNCTIONAL PIN DESCRIPTION The following paragraphs give a description of the general function of each pin assigned in Fig. 1-2 and Fig. 1-3. 1.4.1 VDD AND VSS Power is supplied to the MCU through VDD and VSS. VDD is the positive supply, and VSS is ground. The MCU operates from a single power supply. Very fast signal transitions occur on the MCU pins. The short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care should be taken to provide good power supply bypassing at the MCU by using bypass capacitors with good high-frequency characteristics that are positioned as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded. 1.4.2 OSC1, OSC2 The OSC1 and OSC2 pins are the connections for the on-chip oscillator. The OSC1 and OSC2 pins can accept the following sets of components: 1. A crystal as shown in Figure 1-3(a) 2. A ceramic resonator as shown in Figure 1-3(a) 3. An external clock signal as shown in Figure 1-3(b) The frequency, fOSC, of the oscillator or external clock source is divided by two to produce the internal operating frequency, fOP. If the internal operating frequency is 3MHz, then the external oscillator frequency will be 6MHz. For LS USB 1.5MHz
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February 24, 1999 GENERAL RELEASE SPECIFICATION
frequency clock can be derived from a divided by 4 circuit. The type of oscillator is selected by a mask option. An internal 2M resistor may be selected between OSC1 and OSC2 by a mask option (crystal/ceramic resonator mode only). Crystal Oscillator The circuit in Figure 1-3(a) shows a typical oscillator circuit for an AT-cut, parallel resonant crystal. The crystal manufacturer's recommendations should be followed, as the crystal parameters determine the external component values required to provide maximum stability and reliable start-up. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The crystal and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. An internal start-up resistor of approximately 2 M is provided between OSC1 and OSC2 for the crystal type oscillator as a mask option.
MCU MCU
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OSC1 2M
OSC2
OSC1
OSC2
Unconnected
External Clock (a) Crystal or Ceramic Resonator Connections (b) External Clock Source Connection
Figure 1-3. Oscillator Connections Ceramic Resonator Oscillator In cost-sensitive applications, a ceramic resonator can be used in place of the crystal. The circuit in Figure 1-3(a) can be used for a ceramic resonator. The resonator manufacturer's recommendations should be followed, as the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances. The ceramic resonator and components should be mounted as close as possible to the pins for start-up stabilization and to minimize output distortion. An internal start-up resistor of approximately 2 M is provided between OSC1 and OSC2 for the ceramic resonator type oscillator as a mask option. External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-3(b).This configuration is possible ONLY when the crystal/ceramic resonator mask option is selected.
MC68HC05JB4 REV 2 GENERAL DESCRIPTION For More Information On This Product, Go to: www.freescale.com MOTOROLA 1-5
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
1.4.3 RESET This is an I/O pin. This pin can be used as an input to reset the MCU to a known start-up state by pulling it to the low state. The RESET pin contains a steering diode to discharge any voltage on the pin to VDD, when the power is removed. An internal pull-up is also connected between this pin and VDD. The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. This pin is an output pin if LVR triggers an internal reset. 1.4.4 IRQ (MASKABLE INTERRUPT REQUEST) This input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ interrupt function has a mask option to provide either only negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering. If the option is selected to include level-sensitive triggering, the IRQ input requires an external resistor to VDD for "wired-OR" operation, if desired. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. NOTE Each of the PA0 thru PA3 I/O pins may be connected as an OR function with the IRQ interrupt function by a mask option. This capability allows keyboard scan applications where the transitions or levels on the I/O pins will behave the same as the IRQ pin. The edge or level sensitivity selected by a separate mask option for the IRQ pin also applies to the I/O pins OR'ed to create the IRQ signal. 1.4.5 V3.3 This is an output reference voltage nominally set at 3.3 volt DC. 1.4.6 D+ and D- These two lines carry the USB differential data. For low speed device such as MC68HC05JB4, a 1.5 k resistor is required to be connected across D- and 3.3V for proper signal termination. 1.4.7 PA0-PA7 These eight I/O lines comprise Port-A. PA0 to PA7 are push-pull pins with internal pull-up resistors. The state of any pin is software programmable and all Port A lines are configured as inputs during power-on or reset. The internal pull-up resistor on PA0-4 is software enable. The PA0 thru PA3 can be connected via an internal NAND gate to the IRQ interrupt function enabled by a mask option. PA5 thru PA7 has built in 10mA pull-down device for direct LED drive. In addition, PA6 and PA7 both have Slow Falling Edge Control which is enabled by software and can sink 25mA current selectable by mask option. PA0 thru PA4 have built-in schmitt triggered input. PA4 can be used as an extra interrupt pin (IRQ2) when IRQ2 interrupt is enabled.
MOTOROLA 1-6 GENERAL DESCRIPTION For More Information On This Product, Go to: www.freescale.com MC68HC05JB4 REV 2
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
1.4.8 PB0-PB4 These five I/O lines comprise Port-B. PB0 to PB4 are push-pull pins with internal pull-up resistors. The state of any pin is software programmable and all Port B lines are configured as inputs during power-on or reset. The internal pull-up resistor is software enable. In addition, all Port-B pins have Slow Falling Edge Control which is enabled by software. PB0 can be used as the input capture pin when the input capture function is enabled on the 16-bit Timer. PB0 has built-in schmitt triggered input. When the ADC function is enabled, PB3 and PB4 can be used as extra two analog input channels (AD4 and AD5 respectively) to the ADC. 1.4.9 PC0-PC5
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These six I/O lines comprise Port-C. PC0 to PC5 are push-pull pins. The state of any pin is software programmable and all Port C lines are configured as inputs during power-on or reset. When the ADC function is enabled, PC0 thru PC3 become the four analog input channels to the ADC and PC4 and PC5 become the analog "High" and "Low" reference voltages to the ADC respectively.
MC68HC05JB4 REV 2
GENERAL DESCRIPTION For More Information On This Product, Go to: www.freescale.com
MOTOROLA 1-7
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
Freescale Semiconductor, Inc...
MOTOROLA 1-8
GENERAL DESCRIPTION For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
SECTION 2 MEMORY
The MC68HC05JB4 has 8k-bytes of addressable memory, with 64 bytes of I/O, 176 bytes of user RAM, and 3584 bytes of user ROM, as shown in Figure 2-1.
$0000 $0000 I/O Registers 64 Bytes $003F $0040 $007F $0080 User RAM 176 Bytes $00C0 64 Byte Stack $00FF $012F $0130 Unused 3792 Bytes $0FFF $1000 User ROM 3584 Bytes $1DFF $1E00 $1FEF $1FF0 $1FFF I/O Registers Unused 64 Bytes 64 Bytes $003F
Freescale Semiconductor, Inc...
Reserved Reserved Reserved Reserved
MFT Vector (High Byte) MFT Vector (Low Byte) Timer1 Vector (High Byte) Timer1 Vector (Low Byte) USB Vector (High Byte) USB Vector (Low Byte) IRQ/IRQ2 Vector (High Byte) IRQ/IRQ2 Vector (Low Byte)
$1FF0 $1FF1 $1FF2 $1FF3 $1FF4 $1FF5 $1FF6 $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF
Self-Check ROM 496 Bytes User Vectors 16 Bytes
SWI Vector (High Byte) SWI Vector (Low Byte) Reset Vector (High Byte) Reset Vector (Low Byte)
Figure 2-1. MC68HC05JB4 Memory Map
MC68HC05JB4 REV 2
MEMORY For More Information On This Product, Go to: www.freescale.com
MOTOROLA 2-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
2.1
I/O AND CONTROL REGISTERS The I/O and Control Registers reside in locations $0000 to $003F. The bit assignments for each register are shown in Figure 2-2, Figure 2-3, Figure 2-4, and Figure 2-5. Reading from unused bits will return unknown states, and writing to unused bits will be ignored.
2.2
RAM The user RAM consists of 176 bytes (including the stack) at locations $0080 to $012F. The stack begins at address $00FF and proceeds down to $00C0. Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call.
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2.3
ROM There are a total of 4k bytes of ROM on chip. This includes 3584 bytes of user ROM with locations $1000 to $1DFF for user program storage and 16 bytes for user vectors at locations $1FF0 to $1FFF. Also, 496 bytes of Self-check ROM on chip at locations $1E00 to $1FEF.
MOTOROLA 2-2
MEMORY For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
2.4
ADDR
$0000 $0001 $0002
I/O REGISTERS SUMMARY
REGISTER
Port A Data PORTA Port B Data PORTB Port C Data PORTC
R/W
R W R W R W
BIT 7
PA7 0 0
BIT 6
PA6 0 0
BIT 5
PA5 0
BIT 4
PA4 PB4 PC4
BIT 3
PA3 PB3 PC3
BIT 2
PA2 PB2 PC2
BIT 1
PA1 PB1 PC1
BIT 0
PA0 PB0 PC0
PC5
$0003
$0004 $0005 $0006
Unused
Port A Data Direction DDRA Port B Data Direction DDRB Port C Data Direction DDRC
R W
R W R W R W DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 SLOWEASLOWEB 0 0 0 DDRB4 DDRB3 DDRA2 DDRB2 DDRA1 DDRB1 DDRA0 DDRB0
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DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
$0007
$0008
Unused
MFT Ctrl/Status TCSR
R W
R W TOF RTIF TOFE RTIE 0 TOFR 0 RTIFR RT1 RT0
Figure 2-2. MC68HC05JB4 I/O Registers $0000-$000F
$0009 $000A MFT Counter TCNT IRQ Control/Status ICSR R W R W IRQE IRQ2E 0 0 IRQF IRQ2F 0 IRQR 0 IRQ2R TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0
$000B $000C $000D
$000E $000F
Unused Unused Unused
ADC Control/Status ADSCR ADC Data ADDR
R W R W R W
R W R W unused bits reserved bits COCO ADRC ADON 0 CH3 CH2 ADDR2 CH1 ADDR1 CH0 ADDR0
ADDR7 ADDR6 ADDR5 ADDR4 ADDR3
MC68HC05JB4 REV 2
MEMORY For More Information On This Product, Go to: www.freescale.com
MOTOROLA 2-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
ADDR
$0010 $0011 $0012 $0013 $0014
REGISTER
Port A Pull-Up PURA Port B Pull-Up PURB Timer1 Control TCR Timer1 Status TSR Input Capture MSB ICH Input Capture LSB ICL Output Compare MSB OCH Output Compare LSB OCL Timer1 Counter MSB TCNTH Timer1 Counter LSB TCNTL Alter. Counter MSB ACNTH Alter. Counter LSB ACNTL
R/W
R W R W R W R W R W R W R W R W R W R W R W R W
BIT 7
PURA7
BIT 6
PURA6
BIT 5
PURA5
BIT 4
PURA4 PURB4
BIT 3
PURA3 PURB3 0 0 ICH3 ICL3
BIT 2
PURA2 PURB2 0 0 ICH2 ICL2
BIT 1
PURA1 PURB1 IEDG 0 ICH1 ICL1
BIT 0
PURA0 PURB0 0 0 ICH0 ICL0
ICIE ICF ICH7 ICL7
OCIE OCF ICH6 ICL6
TOIE TOF ICH5 ICL5
0 0 ICH4 ICL4
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$0015 $0016 $0017 $0018 $0019 $001A $001B
OCH7 OCL7
OCH6 OCL6
OCH5 OCL5
OCH4 OCL4
OCH3 OCL3
OCH2 OCL2
OCH1 OCL1
OCH0 OCL0
TCNTH7 TCNTH6 TCNTH5 TCNTH4 TCNTH3 TCNTH2 TCNTH1 TCNTH0 TCNTL7 TCNTL6 TCNTL5 TCNTL4 TCNTL3 TCNTL2 TCNTL1 TCNTL0 ACNTH7 ACNTH6 ACNTH5 ACNTH4 ACNTH3 ACNTH2 ACNTH1 ACNTH0 ACNTL7 ACNTL6 ACNTL5 ACNTL4 ACNTL3 ACNTL2 ACNTL1 ACNTL0
$001C $001D $001E $001F
Unused Unused Unused Unused
R W R W R W R W
unused bits reserved bits
Figure 2-3. MC68HC05JB4 I/O Registers $0010-$001F
MOTOROLA 2-4
MEMORY For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
ADDR
$0020 $0021 $0022 $0023 $0024
REGISTER
USB Endpoint 0 Data 0
R/W
R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 UE1RD7 UE1RD6 UE1RD5 UE1RD4 UE1RD3 UE1RD2 UE1RD1 UE1RD0 UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 UE1RD7 UE1RD6 UE1RD5 UE1RD4 UE1RD3 UE1RD2 UE1RD1 UE1RD0 UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 UE1RD7 UE1RD6 UE1RD5 UE1RD4 UE1RD3 UE1RD2 UE1RD1 UE1RD0 UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 UE1RD7 UE1RD6 UE1RD5 UE1RD4 UE1RD3 UE1RD2 UE1RD1 UE1RD0 UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 UE1RD7 UE1RD6 UE1RD5 UE1RD4 UE1RD3 UE1RD2 UE1RD1 UE1RD0 UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 UE1RD7 UE1RD6 UE1RD5 UE1RD4 UE1RD3 UE1RD2 UE1RD1 UE1RD0 UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 UE1RD7 UE1RD6 UE1RD5 UE1RD4 UE1RD3 UE1RD2 UE1RD1 UE1RD0 UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 UE1RD7 UE1RD6 UE1RD5 UE1RD4 UE1RD3 UE1RD2 UE1RD1 UE1RD0 UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 unused bits reserved bits
UD0R0
USB Endpoint 0 Data 1
UD0R1
USB Endpoint 0 Data 2
UD0R2
USB Endpoint 0 Data 3
UD0R3
USB Endpoint 0 Data 4
UD0R4
USB Endpoint 0 Data 5
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$0025 $0026 $0027 $0028 $0029 $002A $002B $002C $002D $002E $002F
UD0R5
USB Endpoint 0 Data 6
UD0R6
USB Endpoint 0 Data 7
UD0R7
USB Endpoint 1 Data 0
UD1R0
USB Endpoint 1 Data 1
UD1R1
USB Endpoint 1 Data 2
UD1R2
USB Endpoint 1 Data 3
UD1R3
USB Endpoint 1 Data 4
UD1R4
USB Endpoint 1 Data 5
UD1R5
USB Endpoint 1 Data 6
UD1R6
USB Endpoint 1 Data 7
UD1R7
Figure 2-4. MC68HC05JB4 I/O Registers $0020-$002F
MC68HC05JB4 REV 2
MEMORY For More Information On This Product, Go to: www.freescale.com
MOTOROLA 2-5
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
ADDR
$0030 $0031 $0032 $0033 $0034
REGISTER
Unused Unused Unused Unused Unused Unused Unused
USB Control 2 UCR2 USB Address UADR USB Interrupt 0 UIR0 USB Interrupt 1 UIR1 USB Control 0 UCR0 USB Control 1 UCR1 USB Status USR
R/W
R W R W R W R W R W R W R W
R W R W R W R W R W R W R W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
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$0035 $0036
$0037 $0038 $0039 $003A $003B $003C $003D
0 TX1STR
TX1ST
ENABLE2 ENABLE1 STALL2 STALL1
USBEN UADD6 UADD5 UADD4 UADD3 TXD0F 0 TXD1F 0 RXD0F 0 0 RSTF 0 0 TX0E TX1E
UADD2
UADD1 0 0
UADD0 0 0
SUSPND TXD0IE RXD0IE 0
RESUMFR
TXD0FR RXD0FR TXD1FR EOPFR
RXD1F RESUMF
TXD1IE
EOPIE
T0SEQ STALL0 T1SEQ ENDADD RSEQ SETUP
RX0E
TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0
$003E $003F
Reserved Reserved
R W R W
unused bits reserved bits
Figure 2-5. MC68HC05JB4 I/O Registers $0030-$003F
ADDR
$1FF0
REGISTER
COP Register COPR
R/W
R W
BIT 7
0
BIT 6
0
BIT 5
0
BIT 4
0
BIT 3
0
BIT 2
0
BIT 1
0
BIT 0
0 COPR
Figure 2-6. COP Register (COPR)
MOTOROLA 2-6
MEMORY For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
SECTION 3 CENTRAL PROCESSING UNIT
The MC68HC05JB4 has an 8k-bytes memory map. The stack has only 64 bytes. Therefore, the stack pointer has been reduced to only 6 bits and will only decrement down to $00C0 and then wrap-around to $00FF. All other instructions and registers behave as described in this chapter.
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3.1
REGISTERS The MCU contains five registers which are hard-wired within the CPU and are not part of the memory map. These five registers are shown in Figure 3-1 and are described in the following paragraphs.
7
6
5
4
3
2
1
0 A
ACCUMULATOR
15 0
14 0
13 0
12 0
11 0
10 0
9 0
8 0 1 1
INDEX REGISTER
X
STACK POINTER
SP
PROGRAM COUNTER
PC
CONDITION CODE REGISTER
1
1
1
H
I
N
Z
C
CC
HALF-CARRY BIT (FROM BIT 3) INTERRUPT MASK NEGATIVE BIT ZERO BIT CARRY BIT
Figure 3-1. MC68HC05 Programming Model
MC68HC05JB4 REV 2
CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com
MOTOROLA 3-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
3.2
ACCUMULATOR (A) The accumulator is a general purpose 8-bit register as shown in Figure 3-1. The CPU uses the accumulator to hold operands and results of arithmetic calculations or non-arithmetic operations. The accumulator is not affected by a reset of the device.
3.3
INDEX REGISTER (X) The index register shown in Figure 3-1 is an 8-bit register that can perform two functions: * Indexed addressing Temporary storage *
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In indexed addressing with no offset, the index register contains the low byte of the operand address, and the high byte is assumed to be $00. In indexed addressing with an 8-bit offset, the CPU finds the operand address by adding the index register content to an 8-bit immediate value. In indexed addressing with a 16-bit offset, the CPU finds the operand address by adding the index register content to a 16-bit immediate value. The index register can also serve as an auxiliary accumulator for temporary storage. The index register is not affected by a reset of the device. 3.4 STACK POINTER (SP) The stack pointer shown in Figure 3-1 is a 16-bit register. In MCU devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. The stack pointer contains the address of the next free location on the stack. During a reset or the reset stack pointer (RSP) instruction, the stack pointer is set to $00FF. The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled off the stack. When accessing memory, the ten most significant bits are permanently set to 0000000011. The six least significant register bits are appended to these ten fixed bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64($C0) locations. If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies two locations on the stack and an interrupt uses five locations. 3.5 PROGRAM COUNTER (PC) The program counter shown in Figure 3-1 is a 16-bit register. In MCU devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. The program counter contains the address of the next instruction or operand to be fetched.
MOTOROLA 3-2
CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
Normally, the address in the program counter increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. 3.6 CONDITION CODE REGISTER (CCR) The CCR shown in Figure 3-1 is a 5-bit register in which four bits are used to indicate the results of the instruction just executed. The fifth bit is the interrupt mask. These bits can be individually tested by a program, and specific actions can be taken as a result of their states. The condition code register should be thought of as having three additional upper bits that are always ones. Only the interrupt mask is affected by a reset of the device. The following paragraphs explain the functions of the lower five bits of the condition code register. 3.6.1 Half Carry Bit (H-Bit) When the half-carry bit is set, it means that a carry occurred between bits 3 and 4 of the accumulator during the last ADD or ADC (add with carry) operation. The half-carry bit is required for binary-coded decimal (BCD) arithmetic operations. 3.6.2 Interrupt Mask (I-Bit) When the interrupt mask is set, the internal and external interrupts are disabled. Interrupts are enabled when the interrupt mask is cleared. When an interrupt occurs, the interrupt mask is automatically set after the CPU registers are saved on the stack, but before the interrupt vector is fetched. If an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the interrupt is processed as soon as the interrupt mask is cleared. A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt mask to its state before the interrupt was encountered. After any reset, the interrupt mask is set and can only be cleared by the Clear I-Bit (CLI), or WAIT instructions. 3.6.3 Negative Bit (N-Bit) The negative bit is set when the result of the last arithmetic operation, logical operation, or data manipulation was negative. (Bit 7 of the result was a logical one.) The negative bit can also be used to check an often tested flag by assigning the flag to bit 7 of a register or memory location. Loading the accumulator with the contents of that register or location then sets or clears the negative bit according to the state of the flag. 3.6.4 Zero Bit (Z-Bit) The zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or data load operation was zero.
MC68HC05JB4 REV 2 CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com MOTOROLA 3-3
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
3.6.5 Carry/Borrow Bit (C-Bit) The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. This bit is neither set by an INC nor by a DEC instruction.
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MOTOROLA 3-4
CENTRAL PROCESSING UNIT For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
SECTION 4 INTERRUPTS
The MCU can be interrupted in seven different ways: * * Non-maskable Software Interrupt Instruction (SWI) External Asynchronous Interrupt (IRQ) External Asynchronous Interrupt (IRQ2) Optional External Interrupt via IRQ on PA0-PA3 (by a mask option) USB Interrupt Timer1 Interrupt (16-bit Timer) Multi-Function Timer Interrupt
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* * * * * 4.1
INTERRUPT VECTORS Table 4-1. Reset/Interrupt Vector Addresses
Function
Source
Power-On Logic RESET Pin Low Voltage Reset Illegal Address Reset COP Watchdog
Control Bit
Global Hardware Mask
Local Software Mask
Priority (1 = Highest)
Vector Address
Reset
--
--
--
1
$1FFE-$1FFF
Software Interrupt (SWI) External Interrupt (IRQ) USB Interrupts Timer1 Interrupts MFT Interrupts
User Code IRQ Pin IRQ2 Pin TXD0F TXD1F RESUMP ICF Bit OCF Bit TOF Bit TOF Bit RTIF
-- --
-- I Bit
-- IRQE Bit IRQ2E Bit TXD0IE TXD1IE -- ICIE Bit OCIE Bit TOIE Bit TOFE Bit RTIE Bit
Same Priority As Instruction 2
$1FFC-$1FFD $1FFA-$1FFB
--
I Bit
3
$1FF8-$1FF9
--
I Bit
4
$1FF6-$1FF7
--
I Bit
5
$1FF4-$1FF5 $1FF2-$1FF3 $1FF0-$1FF1
Reserved Reserved
MC68HC05JB4 REV 2
INTERRUPTS For More Information On This Product, Go to: www.freescale.com
MOTOROLA 4-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
NOTE If more than one interrupt request is pending, the CPU fetches the vector of the higher priority interrupt first. A higher priority interrupt does not actually interrupt a lower priority interrupt service routine unless the lower priority interrupt service routine clears the I bit. 4.2 INTERRUPT PROCESSING The CPU does the following actions to begin servicing an interrupt: * Stores the CPU registers on the stack in the order shown in Figure 4-1. Sets the I bit in the condition code register to prevent further interrupts. Loads the program counter with the contents of the appropriate interrupt vector locations as shown in Table 4-1.
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* *
The return from interrupt (RTI) instruction causes the CPU to recover its register contents from the stack as shown in Figure 4-1. The sequence of events caused by an interrupt are shown in the flow chart in Figure 4-2.
$0020 $0021 (BOTTOM OF RAM)
$00BE $00BF $00C0 $00C1 $00C2 UNSTACKING ORDER (BOTTOM OF STACK)
n n+1 n+2 n+3 n+4 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PROGRAM COUNTER (HIGH BYTE) PROGRAM COUNTER (LOW BYTE) 5 4 3 2 1 1 2 3 4 5
STACKING $00FD $00FE $00FF TOP OF STACK (RAM) ORDER
Figure 4-1. Interrupt Stacking Order
MOTOROLA 4-2 INTERRUPTS For More Information On This Product, Go to: www.freescale.com MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
I
FROM RESET
YES
I BIT SET? NO
EXTERNAL INTERRUPT? NO
YES
CLEAR IRQ LATCH.
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USB INTERRUPT? NO
YES
TIMER1 INTERRUPT? NO
YES
MFT INTERRUPT? NO
YES
STACK PCL, PCH, X, A, CCR. SET I BIT. LOAD PC WITH INTERRUPT VECTOR.
FETCH NEXT INSTRUCTION.
SWI INSTRUCTION? NO
YES
RTI INSTRUCTION? NO
YES
UNSTACK CCR, A, X, PCH, PCL.
EXECUTE INSTRUCTION.
Figure 4-2. Interrupt Flowchart
MC68HC05JB4 REV 2
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MOTOROLA 4-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
4.3
RESET INTERRUPT SEQUENCE The RESET function is not in the strictest sense an interrupt; however, it is acted upon in a similar manner as shown in Figure 4-2. A low level input on the RESET pin or an internally generated RST signal causes the program to vector to its starting address which is specified by the contents of memory locations $1FFE and $1FFF. The I-bit in the condition code register is also set.
4.4
SOFTWARE INTERRUPT (SWI) The SWI is an executable instruction and a non-maskable interrupt since it is executed regardless of the state of the I-bit in the CCR. As with any instruction, interrupts pending during the previous instruction will be serviced before the SWI opcode is fetched. The interrupt service routine address is specified by the contents of memory locations $1FFC and $1FFD.
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4.5
HARDWARE INTERRUPTS All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing the I-bit enables the hardware interrupts. There are two types of hardware interrupts which are explained in the following sections.
4.5.1 External Interrupt IRQ The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of the IRQ logic is shown in Figure 4-3. The IRQ pin is one source of an IRQ interrupt and a mask option can also enable the four lower Port A pins (PA0 to PA3) to act as other IRQ interrupt sources. Refer to Figure 4-3 for the following descriptions. IRQ interrupt source comes from IRQ latch. The IRQ latch will be set on the falling edge of the IRQ pin or on any falling edge of PA0-3 pins if PA0-3 interrupts have been enabled. If `edge-only' sensitivity is chosen by a mask option, only the IRQ latch output can activate an IRQF flag which creates a request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to the following cases: 1. Falling edge on the IRQ pin. 2. Falling edge on any PA0-PA3 pin with IRQ enabled (via mask option). If level sensitivity is chosen, the active high state of the signal to the clock input of the IRQ latch can also activate an IRQF flag which creates an IRQ request to the CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensitive to the following cases: 1. Low level on the IRQ pin. 2. Falling edge on the IRQ pin. 3. Low level on any PA0- PA3 pin with IRQ enabled (via mask option). 4. Falling edge on any PA0- PA3 pin with IRQ enabled (via mask option).
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The IRQE enable bit controls whether an active IRQF flag can generate an IRQ interrupt sequence. This interrupt is serviced by the interrupt service routine located at the address specified by the contents of $1FFA and $1FFB. If IRQF is set, the only way to clear this flag is by writing a logic one to the IRQR acknowledge bit in the ICSR. As long as the output state of the IRQF flag bit is active the CPU will continuously re-enter the IRQ interrupt sequence until the active state is removed or the IRQE enable bit is cleared.
TO BIH & BIL INSTRUCTION PROCESSING
IRQ
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VDD
PA0 PA1 PA2 PA3 IRQ Level (Mask Option) Port A External Interrupt (Mask Option)
IRQ LATCH R
EXTERNAL INTERRUPT REQUEST
RST IRQ VECTOR FETCH IRQR IRQE IRQF
IRQ STATUS/CONTROL REGISTER INTERNAL DATA BUS
Figure 4-3. External Interrupt (IRQ) Logic 4.5.2 External Interrupt IRQ2 The IRQ2/PA4 pin provides an asynchronous interrupt to the CPU. When a negative-edge is detected by the schmitt trigger input, an IRQ2 interrupt will be generated if the IRQ2E-bit in the ICSR register is set. This interrupt is serviced by the interrupt service routine located at the address specified by the contents of $1FFA and $1FFB. A block diagram of the IRQ2 function is shown in Figure 4-4.
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MOTOROLA 4-5
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GENERAL RELEASE SPECIFICATION February 24, 1999
VDD
IRQ2 LATCH IRQ2 R IRQ2E IRQ2R ICSR ($0A)
IRQ2 INTERRUPT
Figure 4-4. External Interrupt (IRQ2) Logic
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4.5.3 IRQ Control/Status Register (ICSR) - $0A The IRQ interrupt function is controlled by the ICSR located at $000A. All unused bits in the ICSR will read as logic zeros. The IRQF bit is cleared and IRQE bit is set by reset.
BIT 7 ICSR $000A reset: R W IRQE 1 BIT 6 IRQ2E 0 BIT 5 0 0 BIT 4 0 0 BIT 3 IRQF 0 BIT 2 IRQ2F 0 BIT 1 0 IRQR 0 BIT 0 0 IRQ2R 0
Figure 4-5. IRQ Control and Status Register (ICSR) IRQR -- IRQ Interrupt Acknowledge The IRQR acknowledge bit clears an IRQ interrupt by clearing the IRQ latch. The IRQR acknowledge bit will always read as a logic zero. 1 = Writing a logic one to the IRQR acknowledge bit will clear the IRQ latch. 0 = Writing a logic zero to the IRQR acknowledge bit will have no effect on the IRQ latch. IRQF -- IRQ Interrupt Request Flag Writing to the IRQF flag bit will have no effect on it. If the additional setting of IRQF flag bit is not cleared in the IRQ service routine and the IRQE enable bit remains set the CPU will re-enter the IRQ interrupt sequence continuously until either the IRQF flag bit or the IRQE enable bit is clear. The IRQF latch is cleared by reset. 1 = Indicates that an IRQ request is pending. 0 = Indicates that no IRQ request triggered by pins PA0-3 or IRQ is pending. The IRQF flag bit can be cleared by writing a logic one to the IRQR acknowledge bit to clear the IRQ latch and also conditioning the external IRQ sources to be inactive (if the level sensitive interrupts are enabled via mask option). Doing so before exiting the service routine will mask out additional occurrences of the IRQF.
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IRQE -- IRQ Interrupt Enable The IRQE bit enables/disables the IRQF flag bit to initiate an IRQ interrupt sequence. 1 = Enables IRQ interrupt, that is, the IRQF flag bit can generate an interrupt sequence. Reset sets the IRQE enable bit, thereby enabling IRQ interrupts once the I-bit is cleared. Execution of the STOP or WAIT instructions causes the IRQE bit to be set in order to allow the external IRQ to exit these modes. 0 = The IRQF flag bit cannot generate an interrupt sequence. IRQ2R -- IRQ2 Interrupt Acknowledge
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The IRQ2R acknowledge bit clears an IRQ2 interrupt by clearing the IRQ2 latch. The IRQ2R acknowledge bit will always read as a logic zero. 1 = Writing a logic one to the IRQ2R acknowledge bit will clear the IRQ2 latch. 0 = Writing a logic zero to the IRQ2R acknowledge bit will have no effect on the IRQ2 latch. IRQ2F -- IRQ2 Interrupt Request Flag Writing to the IRQ2F flag bit will have no effect on it. If the additional setting of IRQ2F flag bit is not cleared in the IRQ2 service routine and the IRQ2E enable bit remains set the CPU will re-enter the IRQ2 interrupt sequence continuously until either the IRQ2F flag bit or the IRQ2E enable bit is clear. The IRQ2F latch is cleared by reset. 1 = Indicates that an IRQ2 request is pending. 0 = Indicates that no IRQ2 request triggered by pins PA4. The IRQ2F flag bit can be cleared by writing a logic one to the IRQ2R acknowledge bit to clear the IRQ2 latch. IRQ2E - IRQ2 Interrupt Enable The IRQ2E bit enables/disables the IRQ2F flag bit to initiate an IRQ2 interrupt sequence. 1 = Enables IRQ2 interrupt, that is, the IRQ2F flag bit can generate an interrupt sequence. Reset clears the IRQ2E enable bit. 0 = The IRQ2F flag bit cannot generate an interrupt sequence. 4.5.4 Port A External Interrupts (PA0-PA3, by mask option) The IRQ interrupt can also be triggered by the inputs on the PA0 to PA3 port pins if enabled by a single mask option. If enabled, the lower four bits of Port A can activate the IRQ interrupt function, and the interrupt operation will be the same as for inputs to the IRQ pin. This mask option of PA0-3 interrupt allow all of these input pins to be OR'ed with the input present on the IRQ pin. All PA0 to PA3 pins must be selected as a group as an additional IRQ interrupt. All the PA0-3 interrupt sources are also controlled by the IRQE enable bit.
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NOTE The BIH and BIL instructions will only apply to the level on the IRQ pin itself, and not to the output of the logic OR function with the PA0 to PA3 pins. The state of the individual Port A pins can be checked by reading the appropriate Port A pins as inputs.
NOTE If enabled, the PA0 to PA3 pins will cause an IRQ interrupt only when the corresponding pin is configured as input.
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4.5.5 Timer1 Interrupt (TIMER1) The TIMER1 interrupt is generated by the 16-bit timer when either an overflow or an input capture or output compare has occurred as described in the section on 16-bit timer. The interrupt flags and enable bits for the Timer1 interrupts are located in the Timer1 Control & Status Register (TSR) located at $0012, $0013. The I-bit in the CCR must be clear in order for the TIMER1 interrupt to be enabled. Either of these three interrupts will vector to the same interrupt service routine located at the address specified by the contents of memory locations $1FF6 and $1FF7. 4.5.6 USB Interrupt (USB) The USB interrupt is generated by the USB module as described in the section on Universal Serial Bus. The interrupt enable bits for the USB interrupt are located at bit3-bit2 of UIR0 REG and bit3-bit2 of UIR1 REG. Also Once the device goes into Suspend Mode, any bus activities will cause the USB to generate an interrupt to CPU to come out from the Suspend mode. The I-bit in the CCR must be clear in order for the USB interrupt to be enabled. Either of these two interrupts will vector to the same interrupt service routine located at the address specified by the contents of memory locations $1FF8 and $1FF9. 4.5.7 MFT Interrupt (MFT) The MFT interrupt is generated by the MFT module as described in the section on Multi-function Timer. These interrupts will vector to the same interrupt service routine located at the address specified by the contents of memory locations $1FF4 and $1FF5.
MOTOROLA 4-8
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SECTION 5 RESETS
This section describes the six reset sources and how they initialize the MCU. A reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user defined reset vector address. The following conditions produce a reset:
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* * * * * *
Initial power up of device (power on reset). A logic zero applied to the RESET pin (external reset). Timeout of the COP watchdog (COP reset). Low voltage applied to the device (LVR reset). Fetch of an opcode from an address not in the memory map (illegal address reset). Detection of USB reset signal (USB reset).
Figure 5-1 shows a block diagram of the reset sources and their interaction.
USB RESET DETECTION COP WATCHDOG LOW VOLTAGE RESET VDD POWER-ON RESET ILLEGAL ADDRESS RESET INTERNAL ADDRESS BUS RESET S RST D RESET LATCH R INTERNAL CLOCK TO CPU AND SUBSYSTEMS
Figure 5-1. Reset Sources
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5.1
POWER-ON RESET A positive transition on the VDD pin generates a power-on reset. The power-on reset is strictly for conditions during powering up and cannot be used to detect drops in power supply voltage. A 4064 tCYC (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. If the RESET pin is at logic zero at the end of the multiple tCYC time, the MCU remains in the reset condition until the signal on the RESET pin goes to a logic one.
5.2
EXTERNAL RESET A logic zero applied to the RESET pin for 1.5tCYC generates an external reset. This pin is connected to a Schmitt trigger input gate to provide and upper and lower threshold voltage separated by a minimum amount of hysteresis. The external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active low input will generate the internal RST signal that resets the CPU and peripherals. The RESET pin can also act as an open drain output. It will be pulled to a low state by an internal pulldown device that is activated by three internal reset sources. This RESET pulldown device will only be asserted for 3 - 4 cycles of the internal clock, fOP, or as long as the internal reset source is asserted. When the external RESET pin is asserted, the pulldown device will not be turned on. NOTE Do not connect the RESET pin directly to VDD, as this may overload some power supply designs when the internal pulldown on the RESET pin activates.
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5.3
INTERNAL RESETS The five internally generated resets are the initial power-on reset function, the COP Watchdog timer reset, the low voltage reset, and the illegal address detector. Only the COP Watchdog timer reset, low voltage reset and illegal address detector will also assert the pulldown device on the RESET pin for the duration of the reset function or 3 - 4 internal clock cycles, whichever is longer.
5.3.1 Power-On Reset (POR) The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of 4064 internal processor bus clock cycles after the oscillator becomes active.
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The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the end of the 4064 cycle delay, the RST signal will remain in the reset condition until the other reset condition(s) end. POR will not activate the pulldown device on the RESET pin. VDD must drop below VPOR in order for the internal POR circuit to detect the next rise of VDD. 5.3.2 USB Reset The USB reset is generated by a detection on the USB bus reset signal. For MC68HC05JB4, seeing a single-end zero on its upstream port for 4 to 8 bit times will set RSTF bit in UIR0 register. The detections will also generate the RST signal to reset the CPU and other peripherals in the MCU.
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5.3.3 Computer Operating Properly (COP) Reset The COP watchdog is enabled by a mask option. A timeout of the COP watchdog generates a COP reset. The COP watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. To clear the COP watchdog and prevent a COP reset, write a logic zero to the COPC bit of the COP register at location $1FF0.
BIT 7 COPR $1FF0 reset: R W U U U U U U U 0 BIT 6 0 BIT 5 0 BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 0 COPC 0
U = UNAFFECTED BY RESET
Figure 5-2. COP Watchdog Register (COPR) COPC -- COP Clear COPC is a write-only bit. Periodically writing a logic zero to COPC prevents the COP watchdog from resetting the MCU. Reset clears the COPC bit. 1 = No effect on system. 0 = Reset COP watchdog timer. The COP Watchdog reset will assert the pulldown device to pull the RESET pin low for one cycle of the internal bus clock. See section on Core Timer for detail on COP watchdog timeout periods. 5.3.4 Low Voltage Reset (LVR) The LVR activates the RST reset signal to reset the device when the voltage on the VDD pin falls below the LVR trip voltage. The LVR will assert the pulldown device to pull the RESET pin low one cycle of the internal bus clock. The Low Voltage Reset circuit is enabled by a mask option.
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5.3.5 Illegal Address Reset An opcode fetch from an address that is not in the ROM (locations $1000 to $1FFF) or the RAM (locations $0080 to $012F) generates an illegal address reset. The illegal address reset will assert the pulldown device to pull the RESET pin low for 3 to 4 cycles of the internal bus clock.
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SECTION 6 LOW POWER MODES
There are three modes of operation that reduce power consumption: * * Stop mode Wait mode Data retention mode
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*
Figure 6-1 shows the sequence of events in Stop and Wait modes.
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MOTOROLA 6-1
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STOP
WAIT
STOP EXTERNAL OSCILLATOR, STOP INTERNAL TIMER CLOCK, RESET START-UP DELAY
EXTERNAL OSCILLATOR ACTIVE, INTERNAL TIMER CLOCK ACTIVE
STOP INTERNAL PROCESSOR CLOCK, CLEAR I-BIT IN CCR, SET IRQE IN ICSR
STOP INTERNAL PROCESSOR CLOCK, CLEAR I-BIT IN CCR, SET IRQE IN ICSR
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EXTERNAL RESET? NO IRQ EXTERNAL INTERRUPT? NO IRQ2 EXTERNAL INTERRUPT? NO
YES
YES
EXTERNAL RESET? NO
YES
YES
IRQ EXTERNAL INTERRUPT? NO
YES YES
IRQ2 EXTERNAL INTERRUPT? NO
YES USB INTERRUPT OR RESET? NO YES RESTART EXTERNAL OSCILLATOR, START STABILIZATION DELAY YES END OF YES STABILIZATION DELAY? NO RESTART INTERNAL PROCESSOR CLOCK YES
USB RESET OR INTERRUPT? NO TIMER1 INTERNAL INTERRUPT? NO MFT INTERNAL INTERRUPT? NO
1. LOAD PC WITH RESET VECTOR OR 2. SERVICE INTERRUPT. a. SAVE CPU REGISTERS ON STACK. b. SET I BIT IN CCR. c. LOAD PC WITH INTERRUPT VECTOR.
Figure 6-1. STOP and WAIT Flowchart
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6.1
STOP MODE STOP mode is entered by executing the STOP instruction. This is the lowest power consumption mode of the MCU. In the STOP Mode the internal oscillator is turned off, halting all internal processing. Execution of the STOP instruction automatically clears the I-bit in the Condition Code Register and sets the IRQE enable bit in the IRQ Control/Status Register so that the IRQ external interrupt is enabled. All other registers, including the other bits in the TCSR, and memory remain unaltered. All input/output lines remain unchanged. The MCU can be brought out of the STOP Mode by an IRQ external interrupt, IRQ2 external interrupt or a USB coming out from Suspend Mode Interrupt (Bus activity detection) or an externally generated RESET, USB Reset or an LVR reset. When exiting the STOP Mode the internal oscillator will resume after a 128 or 4064 internal processor clock cycle oscillator stabilization delay.
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6.2
WAIT MODE WAIT mode is entered by executing the WAIT instruction. This places the MCU in a low-power mode, which consumes more power than the STOP Mode. In the WAIT Mode the internal processor clock is halted, suspending all processor and internal bus activity. Execution of the WAIT instruction automatically clears the I-bit in the Condition Code Register and sets the IRQE enable bit in the IRQ Control/ Status Register so that the IRQ external interrupt is enabled. All other registers, memory, and input/output lines remain in their previous states. The WAIT Mode may be exited when an external IRQ, IRQ2, USB, Timer1 or MFT interrupt, an LVR reset, USB reset or an external RESET occurs.
6.3
DATA-RETENTION MODE The Data-Retention mode is only available if the Low Voltage Reset function (mask option) is not enabled. In the data retention mode, the MCU retains RAM contents and CPU register contents at VDD voltages as low as 2.0Vdc. The data retention feature allows the MCU to remain in a low power consumption state during which it retains data, but the CPU cannot execute instructions. The RESET pin must be held low during data-retention mode.
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MOTOROLA 6-3
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MOTOROLA 6-4
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SECTION 7 INPUT/OUTPUT PORTS
In normal operating mode there are 19 usable bidirectional I/O lines arranged as one 8-bit I/O port (Port-A), one 5-bit I/O port (Port-B), and one 6-bit I/O port (Port C). The individual bits in these ports are programmable as either inputs or outputs under software control by the data direction registers (DDRs).
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Each pin on Port-A and Port-B has individual internal pull-up resistor (50k typical) which can be enabled by software. In addition, port pins PA6, PA7, and all port-B pins have built in Slow Falling Edge transition feature. This software selectable feature helps to eliminate EMI noise. Other functions such as high current drive, interrupt, are available on some port pins via mask option. 7.1 SLOW FALLING-EDGE OUTPUT DRIVER When enabled, the slow falling-edge output drive feature has a slow falling edge (drops from 5.0V to 2.2V in 167ns typically, with 50pF load) followed by a fast transition to Vss. The fast transition duration is depending on the strength of the output driver defined for each port.
5.0V
Output Driver
2.2V
50pF
0V 165ns 330ns
Figure 7-1. Slow Falling-edge Output Driver
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7.2
PORT-A Port-A is an 8-bit bi-directional port. The port-A data register is at $0000 and the data direction register (DDRA) is at $0004. Reset does not affect the data registers, but clears the data direction registers, thereby returning the port pins to inputs. Writing a `1' to a DDR bit sets the corresponding port bit to output mode. Each pin in Port-A has an internal pull-up resistor (50k typical) which can be individually enabled by writing a `1' to the corresponding bit in the Port-A pull-up control register at location $0010. PA0 to PA4 have built-in schmitt triggered input to improve noise immunity. PA5 to PA7 port pins each has built in high current drive (10mA sink typical) for direct LED drive. In addition, PA6 and PA7 each has optional 25mA drive which can be enabled by Mask Option. To minimize EME (Electro-Magnetic Emission) noise, PA6 and PA7 has slow output transition which can be enabled by writing a `1' to bit-7 of the Port-B data direction register at location $0005. PA0 to PA3 and PA4 can be used to generate IRQ and IRQ2 interrupts respectively. PA0 to PA3 and PA4 cannot generate interrupts via IRQ and IRQ2 if these port pins are configured as output pins. If the pull-up device is enabled and the port pin is configured as output, the output port becomes an open-drain output with 50k pull-up.
Port-A PURX
0 0 1 1
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Port-A DDRX
0 1 0 1
Pin Configuration
Input Output Push/Pull Input with 50k pull-up Open-drain Output with 50k pull-up
NOTE Enabling or disabling the SLOW edge function on PA6 and PA7 does not change the pin configuration. Reading from an output pin will return the content of the data register. 7.2.1 Port-A Data Register
BIT 7 PTA $0000 reset: R W PA7 0 BIT 6 PA6 0 BIT 5 PA5 0 BIT 4 PA4 0 BIT 3 PA3 0 BIT 2 PA2 0 BIT 1 PA1 0 BIT 0 PA0 0
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7.2.2 Port-A Data Direction Register
BIT 7 DDRA $0004 reset: R W DDRA7 0 BIT 6 DDRA6 0 BIT 5 DDRA5 0 BIT 4 DDRA4 0 BIT 3 DDRA3 0 BIT 2 DDRA2 0 BIT 1 DDRA1 0 BIT 0 DDRA0 0
7.2.3 Port-A Pull-up Control Register
BIT 7 PURA $0010 reset: R W PURA7 0 PURA6 0 PURA5 0 PURA4 0 PURA3 0 PURA2 0 PURA1 0 PURA0 0 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
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7.3
PORT-B Port-B is a 5-bit bi-directional port. The port-B data register is at $0001 and the data direction register (DDRB) is at $0005. Reset does not affect the data registers, but clears the data direction registers, thereby returning the port pins to inputs. Writing a `one' to a DDR bit sets the corresponding port bit to output mode. Each pin in Port-B has an internal pull-up resistor (50k typical) which can be individually enabled by writing a `1' to the corresponding bit in the Port-B pull-up control register at location $0011. All Port-B pins have built in Slow Output edge transition driver which can be enabled by writing a `1' to bit-6 of Port-B data direction register at location $0005. When PB0 is configured as an input, it also serves as the input capture pin for the 16-bit Timer. When configured as output, the input to the input capture will be permanently tied "low" and no input capture can be generated. PB0 has built-in schmitt triggered input to improve noise immunity. PB3 and PB4 also serve as extra ADC inputs, AD4 and AD5. When a port pin is selected as ADC input and the ADON bit is set to `1', the pin will be configured as input pin and its pull-up will be disabled automatically regardless of the status of the DDR-bit. The value of the DDR-bit will not be affected. If the pull-up device is enabled and the port pin is configured as output, the output port becomes an open-drain output with 50k pull-up.
Port-B PURX
0 0 1 1
Port-B DDRX
0 1 0 1
Pin Configuration
Input Output Push/Pull Input with 50k pull-up Open-drain Output with 50k pull-up
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NOTE Enabling or disabling the SLOW edge function does not change the pin configuration. Reading from an output pin will return the content of the data register. 7.3.1 Port-B Data Register
BIT 7 PTB $0001 R W 0 0 0 reset: 0 BIT 6 0 BIT 5 0 BIT 4 PB4 0 BIT 3 PB3 0 BIT 2 PB2 0 BIT 1 PB1 0 BIT 0 PB0 0
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7.3.2 Port-B Data Direction Register
BIT 7 DDRB $0005 reset: R W BIT 6 BIT 5 0 0 BIT 4 DDRB4 0 BIT 3 DDRB3 0 BIT 2 DDRB2 0 BIT 1 DDRB1 0 BIT 0 DDRB0 0
SLOWEA SLOWEB 0 0
SLOWEA 1 = Enable slow falling-edge output transition feature on PA6 and PA7. 0 = Disable slow falling-edge output transition feature on PA6 and PA7. SLOWEB 1 = Enable slow falling-edge output transition feature on PB0 to PB4. 0 = Disable slow falling-edge output transition feature on PB0 to PB4. 7.3.3 Port-B Pull-up Control Register
BIT 7 PURB $0011 reset: R W 0 0 0 PURB4 0 PURB3 0 PURB2 0 PURB1 0 PURB0 0 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
7.4
PORT-C Port-C is a 6-bit bi-directional port. The port-C data register is at $0002 and the data direction register (DDRC) is at $0006. Reset does not affect the data registers, but clears the data direction registers, thereby returning the port pins to inputs. Writing a `one' to a DDR bit sets the corresponding port bit to output mode. When the ADON-bit is set, PC4 and PC5 are used as dedicated ADC reference input, reference high (VRH) and reference low (VRL) respectively. And PC0 to PC3 can be used as ADC inputs AD0 to AD3 when the appropriate channel is
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selected. When a port pin is selected as ADC input and the ADON bit is set to `1', the pin will be configured as input pin automatically regardless of the status of the DDR-bit. The value of the DDR-bit will not be affected.
Port-C DDRX
0 1
Pin Configuration
Input Output Push/Pull
NOTE Reading from an output pin will return the content of the data register.
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7.4.1 Port-C Data Register
BIT 7 PTC $0002 reset: R W 0 0 0 BIT 6 0 BIT 5 PC5 0 BIT 4 PC4 0 BIT 3 PC3 0 BIT 2 PC2 0 BIT 1 PC1 0 BIT 0 PC0 0
7.4.2 Port-C Data Direction Register
BIT 7 DDRC $0006 reset: R W 0 0 0 BIT 6 0 BIT 5 DDRC5 0 BIT 4 DDRC4 0 BIT 3 DDRC3 0 BIT 2 DDRC2 0 BIT 1 DDRC1 0 BIT 0 DDRC0 0
MC68HC05JB4 REV 2
INPUT/OUTPUT PORTS For More Information On This Product, Go to: www.freescale.com
MOTOROLA 7-5
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
Freescale Semiconductor, Inc...
MOTOROLA 7-6
INPUT/OUTPUT PORTS For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
SECTION 8 MULTI-FUNCTION TIMER
The Multi-Function Timer module is a 15-stage ripple counter with Timer Over Flow (TOF), Real Time Interrupt (RTI), and COP Watchdog function.
MCU Internal Bus
Freescale Semiconductor, Inc...
8
8 Timer Counter Register ($09) fOP/22 /4 Internal Timer Clock (NTF1)
/210 7-bit counter
/217
/216
/215
/214
RTI Select Circuit
Overflow Detect Circuit
Timer Control & Status Register ($08) TOF RTIF TOFE RTIE TOFR RTIFR RT1 RT0
COP Watchdog Resetable Timer (/8)
Interrupt Circuit
to CPU interrupt
Figure 8-1. Multi-Function Timer Block Diagram
MC68HC05JB4 REV 2
MULTI-FUNCTION TIMER For More Information On This Product, Go to: www.freescale.com
MOTOROLA 8-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
8.1
OVERVIEW As shown in Figure 8-1, the Timer is driven by the timer clock, NTF1, divided by four. NTF1 has the same phase and frequency as the processor bus clock, PH2, but continues to run in WAIT mode. The NTF1 drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the Timer Counter Register (TCNT) at address $09. A timer overflow function is implemented on the last stage of this 8-bit counter, giving a possible interrupt rate of fOP /1024. The last stage of the 8-bit counter also drives a further 7-bit counter. The final four stages is used by the RTI circuit, giving possible RTI rates of fOP /214, 215, 216 or 217, selected by RT1 and RT0 (see Table 8-1). The RTI rate selector bits, and the RTI and TOF enable bits and flags are located in the Timer Control and Status Register at location $08. The power-on cycle clears the entire counter chain and begins clocking the counter. After 128 or 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer will start counting up from zero and normal device operation will begin. If RESET is asserted at any time during operation the counter chain will be cleared.
Freescale Semiconductor, Inc...
8.2
COMPUTER OPERATING PROPERLY (COP) WATCHDOG The COP Watchdog is enabled by a mask option. The COP Watchdog Timer function is implemented by using the output of the RTI circuit and further dividing it by eight. The minimum COP reset rates are listed in Table 8-1. If the COP circuit times out, an internal reset is generated and the normal reset vector is fetched. Preventing a COP time-out is done by writing a "0" to bit-0 of address $1FF0. When the COP is cleared, only the final divide by eight stage (output of the RTI) is cleared. Table 8-1. RTI and COP Rates at fOP =3.0MHz
Bus Frequency, fBUS =fOP =3.0 MHz
RT1 0 0 1 1 RT0 0 1 0 1 Divide Ratio 214 215 216 217 RTI Rate 5.46ms 10.92ms 21.85ms 43.69ms COP Reset Period (RTI x 8) 43.68ms 87.36ms 174.8ms 349.52ms
MOTOROLA 8-2
MULTI-FUNCTION TIMER For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
8.3
MFT REGISTERS
8.3.1 Timer Counter Register (TCNT) $09 The Timer Counter Register is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at fOP /4 and can be used for various functions including a software input capture. Extended time periods can be attained using the TOF function to increment a temporary RAM storage location thereby simulating a 16-bit (or more) counter. The value of each bit of the TCNT is shown in Figure 8-2. This register is cleared by reset.
BIT 7 BIT 6 TMR6 0 BIT 5 TMR5 0 BIT 4 TMR4 0 BIT 3 TMR3 0 BIT 2 TMR2 0 BIT 1 TMR1 0 BIT 0 TMR0 0
Freescale Semiconductor, Inc...
TCNT $0009 reset:
R W
TMR7 0
Figure 8-2. Timer Counter Register 8.3.2 Timer Control/Status Register (TCSR) $08 The TCSR contains the timer interrupt flag bits, the timer interrupt enable bits, and the real time interrupt rate select bits. Bit 2 and bit 3 are write-only bits which will read as logical zeros. Figure 8-3 shows the value of each bit in the TCSR following reset.
BIT 7 TCSR $0008 reset: R W 0 0 TOF BIT 6 RTIF BIT 5 TOFE 0 BIT 4 RTIE 0 BIT 3 0 TOFR 0 BIT 2 0 RTIFR 0 BIT 1 RT1 1 BIT 0 RT0 1
Figure 8-3. Timer Control/Status Register (TCSR) TOF - Timer Overflow Flag The TOF is a read-only flag bit. 1 = Set when the 8-bit ripple counter rolls over from $FF to $00. A TIMER Interrupt request will be generated if TOFE is also set. 0 = Reset by writing a logical one to the TOF acknowledge bit, TOFR. Writing to the TOF flag bit has no effect on its value. This bit is cleared by reset.
MC68HC05JB4 REV 2
MULTI-FUNCTION TIMER For More Information On This Product, Go to: www.freescale.com
MOTOROLA 8-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
RTIF - Real Time Interrupt Flag The RTIF is a read-only flag bit. 1 = Set when the output of the chosen (1 of 4 selections) Real Time Interrupt stage goes active. A TIMER Interrupt request will be generated if RTIE is also set. 0 = Reset by writing a logical one to the RTIF acknowledge bit, RTIFR. Writing to the RTIF flag bit has no effect on its value. This bit is cleared by reset. TOFE - Timer Overflow Enable The TOFE is an enable bit that allows generation of a TIMER Interrupt upon overflow of the Timer Counter Register. 1 = When set, the TIMER Interrupt is generated when the TOF flag bit is set. 0 = When cleared, no TIMER interrupt caused by TOF bit set will be generated. This bit is cleared by reset. RTIE - Real Time Interrupt Enable The RTIE is an enable bit that allows generation of a TIMER Interrupt by the RTIF bit. 1 = When set, the TIMER Interrupt is generated when the RTIF flag bit is set. 0 = When cleared, no TIMER interrupt caused by RTIF bit set will be generated. This bit is cleared by reset. TOFR - Timer Overflow Acknowledge The TOFR is an acknowledge bit that resets the TOF flag bit. This bit is unaffected by reset. Reading the TOFR will always return a logical zero. 1 = Clears the TOF flag bit. 0 = Does not clear the TOF flag bit. RTIFR - Real Time Interrupt Acknowledge The RTIFR is an acknowledge bit that resets the RTIF flag bit. This bit is unaffected by reset. Reading the RTIFR will always return a logical zero. 1 = Clears the RTIF flag bit. 0 = Does not clear the RTIF flag bit. 8.4 OPERATION DURING STOP MODE When STOP is exited by an external interrupt or an LVR reset or an external RESET, the internal oscillator will resume, followed by a 128 or 4064 internal processor oscillator stabilization delay. 8.5 COP CONSIDERATION DURING STOP MODE In STOP mode, the clock to the Watchdog Timer is stopped and is therefore impossible to generate COP reset when in STOP mode. The COP function will resume 128 or 4064 cycles after exiting from STOP.
MOTOROLA 8-4 MULTI-FUNCTION TIMER For More Information On This Product, Go to: www.freescale.com MC68HC05JB4 REV 2
Freescale Semiconductor, Inc...
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
SECTION 9 16-BIT TIMER
This 16-bit Programmable Timer (Timer1) has an Input Capture function and an Output Compare function. Figure 9-1 shows a block diagram of the 16-bit programmable timer.
Freescale Semiconductor, Inc...
ICAP1
EDGE SELECT & DETECT LOGIC ICF
ICRH ($0014)
ICRL ($0015)
IEDG
TMRH ($0018) TMRL ($0019)
ACRH ($001A) ACRL ($001B)
16-BIT COUNTER OVERFLOW (TOF)
/4
INTERNAL CLOCK (fOSC / 2)
16-BIT COMPARATOR
OCRH ($0016) OCRL ($0017)
OCF
TIMER INTERRUPT REQUEST RESET IEDG OCIE TOIE OCF TOF ICIE ICF
TIMER CONTROL REGISTER $0012 INTERNAL DATA BUS
TIMER STATUS REGISTER $0013
Figure 9-1. Programmable Timer Block Diagram
MC68HC05JB4 REV 2 16-BIT TIMER For More Information On This Product, Go to: www.freescale.com MOTOROLA 9-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
The basis of the 16-bit Timer is a 16-bit free-running counter which increases in count with each internal bus clock cycle. The counter is the timing reference for the input capture and output compare functions. The input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays. Software can read the value in the 16-bit free-running counter at any time without affect the counter sequence. Because of the 16-bit timer architecture, the I/O registers for the input capture and output compare functions are pairs of 8-bit registers. Each register pair contains the high and low byte of that function. Generally, accessing the low byte of a specific timer function allows full control of that function; however, an access of the high byte inhibits that specific timer function until the low byte is also accessed. Because the counter is 16 bits long and preceded by a fixed divide-by-four prescaler, the counter rolls over every 262,144 internal clock cycles. Timer resolution with a 4MHz crystal oscillator is 2 microsecond/count. The interrupt capability, the input capture edge, and the output compare state are controlled by the timer control register (TCR) located at $0012 and the status of the interrupt flags can be read from the timer status register (TSR) located at $0013. 9.1 TIMER REGISTERS (TMRH, TMRL) The functional block diagram of the 16-bit free-running timer counter and timer registers is shown in Figure 9-2. The timer registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
Freescale Semiconductor, Inc...
LATCH
TMRL ($0019)
READ TMRL
READ TMRH RESET
READ ($FFFC)
TMRH ($0018)
TMR LSB /4 INTERNAL CLOCK (fOSC / 2) TIMER INTERRUPT REQUEST TOF TIMER STATUS REG. $0013 INTERNAL DATA BUS
16-BIT COUNTER
OVERFLOW (TOF)
TIMER CONTROL REG. $0012
Figure 9-2. Programmable Timer Counter Block Diagram
MOTOROLA 9-2
TOIE
16-BIT TIMER For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
The timer registers (TMRH, TMRL) shown in Figure 9-3 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the timer registers has no effect. Reset of the device presets the timer counter to $FFFC.
BIT 7 TMRH $0018 reset: TMRL $0019 reset: R W 1 1 1 1 1 1 0 0 R W 1 TMRL7 1 TMRL6 1 TMRL5 1 TMRL4 1 TMRL3 1 TMRL2 1 TMRL1 1 TMRL0 TMRH7 BIT 6 TMRH6 BIT 5 TMRH5 BIT 4 TMRH4 BIT 3 TMRH3 BIT 2 TMRH2 BIT 1 TMRH1 BIT 0 TMRH0
Freescale Semiconductor, Inc...
Figure 9-3. Programmable Timer Counter Registers (TMRH, TMRL) The TMRL latch is a transparent read of the LSB until the a read of the TMRH takes place. A read of the TMRH latches the LSB into the TMRL location until the TMRL is again read. The latched value remains fixed even if multiple reads of the TMRH take place before the next read of the TMRL. Therefore, when reading the MSB of the timer at TMRH the LSB of the timer at TMRL must also be read to complete the read sequence. During power-on-reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator start-up delay. Because the counter is sixteen bits and preceded by a fixed divide-by-four prescaler, the value in the counter repeats every 262, 144 internal bus clock cycles (524, 288 oscillator cycles). When the free-running counter rolls over from $FFFF to $0000, the timer overflow flag bit (TOF) is set in the TSR. When the TOF is set, it can generate an interrupt if the timer overflow interrupt enable bit (TOIE) is also set in the TCR. The TOF flag bit can only be reset by reading the TMRL after reading the TSR. Other than clearing any possible TOF flags, reading the TMRH and TMRL in any order or any number of times does not have any effect on the 16-bit free-running counter. NOTE To prevent interrupts from occurring between readings of the TMRH and TMRL, set the I bit in the condition code register (CCR) before reading TMRH and clear the I bit after reading TMRL.
MC68HC05JB4 REV 2
16-BIT TIMER For More Information On This Product, Go to: www.freescale.com
MOTOROLA 9-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
9.2
ALTERNATE COUNTER REGISTERS (ACRH, ACRL) The functional block diagram of the 16-bit free-running timer counter and alternate counter registers is shown in Figure 9-4. The alternate counter registers behave the same as the timer registers, except that any reads of the alternate counter will not have any effect on the TOF flag bit and Timer interrupts. The alternate counter registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
INTERNAL DATA BUS LATCH ACRL ($001B) READ ACRL
Freescale Semiconductor, Inc...
READ ACRH RESET
READ ($FFFC)
ACRH ($001A)
TMR LSB /4 INTERNAL CLOCK (fOSC / 2)
16-BIT COUNTER
Figure 9-4. Alternate Counter Block Diagram The alternate counter registers (ACRH, ACRL) shown in Figure 9-5 are read-only locations which contain the current high and low bytes of the 16-bit free-running counter. Writing to the alternate counter registers has no effect. Reset of the device presets the timer counter to $FFFC.
BIT 7 ACRH $001A reset: ACRL $001B reset: R W 1 1 1 1 1 1 0 0 R W 1 ACRL7 1 ACRL6 1 ACRL5 1 ACRL4 1 ACRL3 1 ACRL2 1 ACRL1 1 ACRL0 ACRH7 BIT 6 ACRH6 BIT 5 ACRH5 BIT 4 ACRH4 BIT 3 ACRH3 BIT 2 ACRH2 BIT 1 ACRH1 BIT 0 ACRH0
Figure 9-5. Alternate Counter Registers (ACRH, ACRL) The ACRL latch is a transparent read of the LSB until the a read of the ACRH takes place. A read of the ACRH latches the LSB into the ACRL location until the ACRL is again read. The latched value remains fixed even if multiple reads of the ACRH take place before the next read of the ACRL. Therefore, when reading the MSB of the timer at ACRH the LSB of the timer at ACRL must also be read to complete the read sequence. During power-on-reset (POR), the counter is initialized to $FFFC and begins counting after the oscillator start-up delay. Because the counter is sixteen bits and preceded by a fixed divide-by-four prescaler, the value in the counter repeats every 262,144 internal bus clock cycles (524,288 oscillator cycles). Reading the ACRH and ACRL in any order or any number of times does not have any effect on the 16-bit free-running counter or the TOF flag bit.
MOTOROLA 9-4 16-BIT TIMER For More Information On This Product, Go to: www.freescale.com MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
NOTE To prevent interrupts from occurring between readings of the ACRH and ACRL, set the I bit in the condition code register (CCR) before reading ACRH and clear the I bit after reading ACRL. 9.3 INPUT CAPTURE REGISTERS The input capture function is a technique whereby an external signal (connected to PB0/ICAP1 pin) is used to trigger the 16-bit timer counter. In this way it is possible to relate the timing of an external signal to the internal counter value, and hence to elapsed time. When the input capture circuitry detects an active edge on the ICAP1 pin, it latches the contents of the free-running timer counter registers into the input capture registers as shown in Figure 9-6. Latching values into the input capture registers at successive edges of the same polarity measures the period of the selected input signal. Latching the counter values at successive edges of opposite polarity measures the pulse width of the signal.
INTERNAL DATA BUS
Freescale Semiconductor, Inc...
READ ICRH EDGE SELECT & DETECT LOGIC ($FFFC) IEDG LATCH ICRH ($0014) ICRL ($0015)
PB0/ICAP1
READ ICRL /4 INTERNAL CLOCK (fOSC / 2) TIMER INTERRUPT REQUEST
16-BIT COUNTER INPUT CAPTURE (ICF)
IEDG
ICIE
RESET
ICF TIMER STATUS REG. $0013 INTERNAL DATA BUS
TIMER CONTROL REG. $0012
Figure 9-6. Timer Input Capture Block Diagram The input capture registers are made up of two 8-bit read-only registers (ICRH, ICRL) as shown in Figure 9-7. The input capture edge detector contains a Schmitt trigger to improve noise immunity. The edge that triggers the counter transfer is defined by the input edge bit (IEDG) in the TCR. Reset does not affect the contents of the input capture registers.
MC68HC05JB4 REV 2 16-BIT TIMER For More Information On This Product, Go to: www.freescale.com MOTOROLA 9-5
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
The result obtained by an input capture will be one count higher than the value of the free-running timer counter preceding the external transition. This delay is required for internal synchronization. Resolution is affected by the prescaler, allowing the free-running timer counter to increment once every four internal clock cycles (eight oscillator clock cycles).
BIT 7 ICRH $0014 reset: ICRL R W U U U U U U U U reset: R W U ICRL7 U ICRL6 U ICRL5 U ICRL4 U ICRL3 U ICRL2 U ICRL1 U ICRL0 ICRH7 BIT 6 ICRH6 BIT 5 ICRH5 BIT 4 ICRH4 BIT 3 ICRH3 BIT 2 ICRH2 BIT 1 ICRH1 BIT 0 ICRH0
Freescale Semiconductor, Inc...
$0015
U = UNAFFECTED BY RESET
Figure 9-7. Input Capture Registers (ICRH, ICRL) Reading the ICRH inhibits further captures until the ICRL is also read. Reading the ICRL after reading the timer status register (TSR) clears the ICF flag bit. does not inhibit transfer of the free-running counter. There is no conflict between reading the ICRL and transfers from the free-running timer counters. The input capture registers always contain the free-running timer counter value which corresponds to the most recent input capture. NOTE To prevent interrupts from occurring between readings of the ICRH and ICRL, set the I bit in the condition code register (CCR) before reading ICRH and clear the I bit after reading ICRL. 9.4 OUTPUT COMPARE REGISTERS The Output Compare function is a means of generating an interrupt when the 16bit timer counter reaches a selected value as shown in Figure 9-8. Software writes the selected value into the output compare registers. On every fourth internal clock cycle (every eight oscillator clock cycle) the output compare circuitry compares the value of the free-running timer counter to the value written in the output compare registers. When a match occurs, the output compare interrupt flag, OCF is set. A timer interrupt request to the CPU is generated if the output compare interrupt enable is set, i.e. OCIE=1. Software can use the output compare register to measure time periods, to generate timing delays, or to generate a pulse of specific duration or a pulse train of specific frequency and duty cycle.
MOTOROLA 9-6
16-BIT TIMER For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
Writing to the OCRH before writing to the OCRL inhibits timer compares until the OCRL is written. Reading or writing to the OCRL after reading the TSR will clear the output compare flag bit (OCF).
R/W OCRH
OCRH ($0016)
OCRL ($0017)
R/W OCRL
16-BIT COMPARATOR
Freescale Semiconductor, Inc...
($FFFC) 16-BIT COUNTER OUTPUT COMPARE (OCF)
/4
INTERNAL CLOCK (fOSC / 2) TIMER INTERRUPT REQUEST
OCIE
RESET
TIMER CONTROL REG. $0012
OCF TIMER STATUS REG. $0013 INTERNAL DATA BUS
Figure 9-8. Timer Output Compare Block Diagram
BIT 7 OCRH $0016 reset: OCRL $0017 reset: R W R W OCRH7 U BIT 6 OCRH6 U BIT 5 OCRH5 U BIT 4 OCRH4 U BIT 3 OCRH3 U BIT 2 OCRH2 U BIT 1 OCRH1 U BIT 0 OCRH0 U
OCRL7 U
OCRL6 U
OCRL5 U
OCRL4 U
OCRL3 U
OCRL2 U
OCRL1 U
OCRL0 U
U = UNAFFECTED BY RESET
Figure 9-9. Output Compare Registers (OCRH, OCRL) To prevent OCF from being set between the time it is read and the time the output compare registers are updated, use the following procedure: 1. Disable interrupts by setting the I bit in the condition code register. 2. Write to the OCRH. Compares are now inhibited until OCRL is written. 3. Read the TSR to arm the OCF for clearing. 4. Enable the output compare registers by writing to the OCRL. This also clears the OCF flag bit in the TSR. 5. Enable interrupts by clearing the I bit in the condition code register.
MC68HC05JB4 REV 2 16-BIT TIMER For More Information On This Product, Go to: www.freescale.com MOTOROLA 9-7
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
A software example of this procedure is shown below.
9B ... ... B7 B6 BF ... ... 9A SEI ... ... STA LDA STX ... ... CLI DISABLE INTERRUPTS ..... ..... INHIBIT OUTPUT COMPARE ARM OCF FLAG FOR CLEARING READY FOR NEXT COMPARE, OCF CLEARED ..... ..... ENABLE INTERRUPTS
16 13 17
OCRH TSR OCRL
9.5
TIMER CONTROL REGISTER (TCR) The timer control register is shown in Figure 9-10 performs the following functions: * * * * Enables input capture interrupts Enables output compare interrupts Enables timer overflow interrupts Control the active edge polarity of the ICAP1 signal on pin PB0/ICAP1
Freescale Semiconductor, Inc...
Reset clears all the bits in the TCR with the exception of the IEDG bit which is unaffected.
BIT 7 TCR $0012 reset: R W ICIE 0 BIT 6 OCIE 0 BIT 5 TOIE 0 BIT 4 0 0 BIT 3 0 0 BIT 2 0 0 BIT 1 IEDG Unaffected BIT 0 0 0
Figure 9-10. Timer Control Register (TCR) ICIE - INPUT CAPTURE INTERRUPT ENABLE This read/write bit enables interrupts caused by an active signal on the PB0/ ICAP1 pin. Reset clears the ICIE bit. 1 = Input capture interrupts enabled. 0 = Input capture interrupts disabled. OCIE - OUTPUT COMPARE INTERRUPT ENABLE This read/write bit enables interrupts caused by a successful compare between the timer counter and the output compare registers. Reset clears the OCIE bit. 1 = Output compare interrupts enabled. 0 = Output compare interrupts disabled. TOIE - TIMER OVERFLOW INTERRUPT ENABLE This read/write bit enables interrupts caused by a timer overflow. Reset clears the TOIE bit. 1 = Timer overflow interrupts enabled. 0 = Timer overflow interrupts disabled.
MOTOROLA 9-8 16-BIT TIMER For More Information On This Product, Go to: www.freescale.com MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
IEDG - INPUT CAPTURE EDGE SELECT The state of this read/write bit determines whether a positive or negative transition on the ICAP1 pin triggers a transfer of the contents of the timer register to the input capture register. Reset has no effect on the IEDG bit. 1 = Positive edge (low to high transition) triggers input capture. 0 = Negative edge (high to low transition) triggers input capture. 9.6 TIMER STATUS REGISTER (TSR) The timer status register (TSR) shown in Figure 9-11 contains flags for the following events: *
Freescale Semiconductor, Inc...
An active signal on the PB0/ICAP1 pin, transferring the contents of the timer registers to the input capture registers. A match between the 16-bit counter and the output compare registers An overflow of the timer registers from $FFFF to $0000.
* *
Writing to any of the bits in the TSR has no effect. Reset does not change the state of any of the flag bits in the TSR.
BIT 7 TSR $0013 reset: R W U U U 0 0 0 0 0 ICF BIT 6 OCF BIT 5 TOF BIT 4 0 BIT 3 0 BIT 2 0 BIT 1 0 BIT 0 0
U = UNAFFECTED BY RESET
Figure 9-11. Timer Status Registers (TSR) ICF - INPUT CAPTURE FLAG The ICF bit is automatically set when an edge of the selected polarity occurs on the PB0/ICAP1 pin. Clear the ICF bit by reading the timer status register with the ICF set, and then reading the low byte (ICRL, $0015) of the input capture registers. Reset has no effect on ICF. OCF - OUTPUT COMPARE FLAG The OCF bit is automatically set when the value of the timer registers matches the contents of the output compare registers. Clear the OCF bit by reading the timer status register with the OCF set, and then accessing the low byte (OCRL, $0017) of the output compare registers. Reset has no effect on OCF. TOF - TIMER OVERFLOW FLAG The TOF bit is automatically set when the 16-bit timer counter rolls over from $FFFF to $0000. Clear the TOF bit by reading the timer status register with the TOF set, and then accessing the low byte (TMRL, $0019) of the timer registers. Reset has no effect on TOF.
MC68HC05JB4 REV 2
16-BIT TIMER For More Information On This Product, Go to: www.freescale.com
MOTOROLA 9-9
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
9.7
TIMER OPERATION DURING WAIT MODE During WAIT mode the 16-bit timer continues to operate normally and may generate an interrupt to trigger the MCU out of the WAIT mode.
9.8
TIMER OPERATION DURING STOP MODE When the MCU enters the STOP mode the free-running counter stops counting (the internal processor clock is stopped). It remains at that particular count value until the STOP mode is exited by applying a low signal to the IRQ pin, at which time the counter resumes from its stopped value as if nothing had happened. If STOP mode is exited via an external reset (logic low applied to the RESET pin) the counter is forced to $FFFC.
Freescale Semiconductor, Inc...
If a valid input capture edge occurs at the PB0/TCAP pin during the STOP mode the input capture detect circuitry will be armed. This action does not set any flags or "wake up" the MCU, but when the MCU does "wake up" there will be an active input capture flag (and data) from the first valid edge. If the STOP mode is exited by an external reset, no input capture flag or data will be present even if a valid input capture edge was detected during the STOP mode.
MOTOROLA 9-10
16-BIT TIMER For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
SECTION 10 UNIVERSAL SERIAL BUS MODULE
This USB Module is designed for USB application in LS products. With minimized software effort, it can fully comply with USB LS device specification. See USB specification version 1.0 for the detail description of USB.
Freescale Semiconductor, Inc...
10.1
FEATURES * * * Integrated 3.3 Volt Regulator with 3.3V Output Pin Integrated USB transceiver supporting Low Speed functions USB Data Control Logic - Packet decoding/generation - CRC generation and checking - NRZI encoding/decoding - Bit-stuffing * * * * * * * * * * * USB reset support Control Endpoint 0 and Interrupt Endpoints 1 and 2 Two 8-byte transmit buffers One 8-byte receive buffer Suspend and resume operations Remote Wake-up support USB generated interrupts transaction interrupt driven Resume interrupt End of Packet interrupt Stall, Nak, and Ack handshake generation
MC68HC05JB4 REV 2
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MOTOROLA 10-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
10.2
OVERVIEW This section provides an overview of the Universal Serial Bus (USB) module in the MC68HC05JB4. This USB module is designed to serve as a low-speed (LS) USB device per the Universal Serial Bus Specification Rev 1.0. Three types of USB data transfers are supported: control, interrupt, and bulk (transmit only). Endpoint 0 functions as a receive/transmit control endpoint. Endpoints 1 and 2 can function as interrupt or bulk, but only in the transmit direction. A block diagram of the USB module is shown Figure 10-1. The USB module manages communications between the host and the USB function. The module is partitioned into four functional blocks. These blocks consist of a 3.3 volt regulator, a dual function transceiver, the USB control logic, and the endpoint registers. The blocks are further detailed in Section 10.4.
Freescale Semiconductor, Inc...
USB CONTROL LOGIC
RCV TRANSCEIVER VPIN VMIN VPOUT VMOUT D+ D- USB Upstream Port
CPU BUS
USB REGISTERS
REGULATOR
3.3V OUT
Figure 10-1. USB Block Diagram 10.2.1 USB Protocol Figure 10-2 shows the various transaction types supported by the MC68HC05JB4 USB module. The transactions are portrayed as error free. The effect of errors in the data flow are discussed later.
MOTOROLA 10-2
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
ENDPOINT 0 TRANSACTIONS:
Control Write
SETUP DATA0 ACK OUT DATA1 ACK
OUT
DATA0
ACK
OUT
DATA0/1
ACK
IN
DATA1
ACK
Control Read
Freescale Semiconductor, Inc...
SETUP
DATA0
ACK
IN
DATA1
ACK
IN
DATA0
ACK
IN
DATA0/1
ACK
OUT
DATA1
ACK
No-Data Control
SETUP DATA0 ACK IN DATA1 ACK
ENDPOINTS 1 & 2 TRANSACTIONS: KEY:
Interrupt
IN DATA0/1 ACK Unrelated Bus Traffic Host Generated Device Generated
Bulk Transmit
IN DATA0/1 ACK
Figure 10-2. Supported Transaction Types per Endpoint Each USB transaction is comprised of a series of packets. The MC68HC05JB4 USB module supports the packet types shown in Figure 10-3. Token packets are generated by the USB host and decoded by the USB device. Data and Handshake packets are both decoded and generated by the USB device depending on the type of transaction.
MC68HC05JB4 REV 2
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MOTOROLA 10-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
Token Packet:
IN OUT SETUP
Data Packet: SYNC PID PID ADDR ENDP CRC5 EOP
DATA0 DATA1
Handshake Packet:
SYNC
PID
PID
DATA 0 - 8 bytes
CRC5
EOP
Freescale Semiconductor, Inc...
ACK NAK STALL
SYNC PID PID EOP
Figure 10-3. Supported USB Packet Types The following sections will give some detail on each segment used to form a complete USB transaction. 10.2.1.1 Sync Pattern The NRZI (See Section 10.4.4.1) bit pattern shown in Figure 10-4 is used as a synchronization pattern and is prefixed to each packet. This pattern is equivalent to a data pattern of seven 0's followed by a 1 (0x80).
SYNC PATTERN NRZI Data Encoding Idle PID0 PID1
Figure 10-4. Sync Pattern The start of a packet (SOP) is signaled by the originating port by driving the D+ and D- lines from the idle state (also referred to as the "J" state) to the opposite logic level (also referred to as the "K" state). This switch in levels represents the first bit of the Sync field. Figure 10-5 shows the data signaling and voltage levels for the start of packet and the sync pattern.
MOTOROLA 10-4
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
VOH (min)
VSE (max) VSE (min) VOL (min) VSS FIRST BIT OF PACKET BUS IDLE SOP END OF SYNC
Freescale Semiconductor, Inc...
Figure 10-5. SOP, Sync Signaling and Voltage Levels 10.2.1.2 Packet Identifier Field The Packet Identifier field is an eight bit number comprised of the four bit packet identification (PID) and its complement. The field follows the sync pattern and determines the direction and type of transaction on the bus. Table 10-1 shows the PID values for the supported packet types. Table 10-1. Supported Packet Identifiers
PID Value %1001 %0001 %1101 %0011 %1011 %0010 %1010 %1110 PID Type IN Token OUT Token SETUP Token DATA0 Packet DATA1 Packet ACK Handshake NAK Handshake STALL Handshake
10.2.1.3 Address Field (ADDR) The Address field is a seven bit number that is used to select a particular USB device. This field is compared to the lower seven bits of the UADDR register to determine if a given transaction is targeting the MC68HC05JB4 USB device.
MC68HC05JB4 REV 2
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MOTOROLA 10-5
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
10.2.1.4 Endpoint Field (ENDP) The Endpoint field is a four bit number that is used to select a particular endpoint within a USB device. For the MC68HC05JB4, this will be a binary number between zero and two inclusive. Any other value will cause the transaction to be ignored. 10.2.1.5 Cyclic Redundancy Check (CRC) Cyclic Redundancy Checks are used to verify the address and data stream of a USB transaction. This field is five bits wide for token packets and sixteen bits wide for data packets. CRCs are generated in the transmitter and sent on the USB data lines after both the endpoint field and the data field. Figure 10-6 shows how the five bit CRC value is calculated from the data stream and verified for the address and endpoint fields of a token packet. Figure 10-7 shows how the sixteen bit CRC value is calculated and either transmitted or verified for the data packet of a given transaction.
Freescale Semiconductor, Inc...
- Update every bit time. - Reset to ones at SOP Data Stream next bit 5
Generator Polynomial: 0 01 0 1 5 0
0
MUX 5
1 Expected Residual: 0 11 0 0
5
5
Good CRC
Y
Equal?
N
Bad CRC
Figure 10-6. CRC Block Diagram for Address and Endpoint Fields
MOTOROLA 10-6
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
- Update every bit time - Reset to ones at SOP Input / Output Data Stream next bit 16
Generator Polynomial: 10 0 00 000 00 00 0 101 16 0
Freescale Semiconductor, Inc...
0 Output Data Stream TRANSMIT
MUX
1
16
CRC16 Transmitted MSB first after final data byte.
16 RECEIVE Expected Residual: 1 0 0 0 0 0 0 0 0 0 00 1 1 01 16
Good CRC Y
Equal?
N
Bad CRC
Figure 10-7. CRC Block Diagram for Data Packets 10.2.1.6 End Of Packet (EOP) The single-ended 0 (SE0) state is used to signal an end of packet (EOP). The single-ended 0 state is indicated by both D+ and D- being below 0.8 V. EOP will be signaled by driving D+ and D- to the single-ended 0 state for two bit times followed by driving the lines to the idle state for one bit time. The transition from the single-ended 0 to the idle state defines the end of the packet. The idle state is asserted for one bit time and then both the D+ and D- output drivers are placed in their high-impedance state. The bus termination resistors hold the bus in the idle state. Figure 10-8 shows the data signaling and voltage levels for an end of packet transaction.
MC68HC05JB4 REV 2
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MOTOROLA 10-7
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
LAST BIT OF PACKET EOP STROBE VOH (min)
BUS DRIVEN TO IDLE STATE BUS FLOATS BUS IDLE
VSE (max) VSE (min) VOL (min) VSS
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Figure 10-8. EOP Transaction Voltage Levels The width of the SE0 in the EOP is about two bit times. The EOP width is measured with the same capacitive load used for maximum rise and fall times and is measured at the same level as the differential signal crossover points of the data lines.
tPeriod DIFFERENTIAL DATA LINES DATA CROSSOVER LEVEL
EOP WIDTH
Figure 10-9. EOP Width Timing 10.2.2 Reset Signaling A reset is signaled on the bus by the presence of an extended SE0 at the USB data pins of a device. The reset signaling is specified to be present for a minimum of 10 ms. An active device (powered and not in the suspend state) seeing a single-ended zero on its USB data inputs for more than 2.5s may treat that signal as a reset, but must have interpreted the signaling as a reset within 5.5 s. For a Low speed device, an SE0 condition between 4 and 8 low speed bit times represents a valid USB reset. A USB sourced reset will hold the MC68HC05JB4 in reset for the duration of the reset on the USB bus. The RSTF bit in the USB interrupt register 0 (UIR0) will be set after the internal reset is removed (See Section 10.5.2 for more detail). After a reset is removed, the device will be in the attached, but not yet addressed or configured state (refer to Section 9.1 of the USB specification). The device must be able to accept a device address via a SET_ADDRESS command (refer to section 9.4 of the USB specification) no later than 10 ms after the reset is removed.
MOTOROLA 10-8 UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
Reset can wake a device from the suspended mode. A device may take up to 10ms to wake up from the suspended state. 10.2.3 Suspend The MC68HC05JB4 supports suspend mode for low power. Suspend mode should be entered when the USB data lines are in the idle state for more than 3.0 ms. Entry into Suspend mode is controlled by the SUSPND bit in the USB Interrupt Register. Any low speed bus activity should keep the device out of the suspend state. Low speed devices are kept awake by periodic low speed EOP signals from the host. This is referred to as Low speed keep alive (refer to Section 11.2.5.1 of the USB specification).
Freescale Semiconductor, Inc...
Firmware should monitor the EOPF flag and enter suspend mode by setting the SUSPND bit if an EOP is not detected for 3 ms. Per the USB specification, the MC68HC05JB4 is required to draw less than 500A from the VDD supply when in the suspend state. This includes the current supplied by the voltage regulator to the 15 K to ground termination resistors placed at the host end of the USB bus. This low current requirement means that firmware is responsible for entering STOP mode once the USB module has been placed in the suspend state. 10.2.4 Resume After Suspend The MC68HC05JB4 can be activated from the suspend state by normal bus activity, a USB reset signal, or by a forced resume driven from the MC68HC05JB4. 10.2.4.1 Host Initiated Resume The host signals resume by initiating resume signalling ("K" state) for at least 20 ms followed by a standard low speed EOP signal. This 20 ms ensures that all devices in the USB network are awakened. After resuming the bus, the host must begin sending bus traffic within 3 ms to prevent the device from re-entering suspend mode. 10.2.4.2 USB Reset Signalling Reset can wake a device from the suspended mode. A device may take up to 10 ms to wake up from the suspended state. 10.2.4.3 Remote Wake-up The MC68HC05JB4 also supports the remote wake-up feature. The firmware has the ability to exit suspend mode by signaling a resume state to the upstream Host or Hub. A non-idle state ("K" state) on the USB data lines is accomplished by asserting the FRESUM bit in the UCR1 register.
MC68HC05JB4 REV 2 UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com MOTOROLA 10-9
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
When using the remote wake-up capability, the firmware must wait for at least 5 ms after the bus is in the idle state before sending the remote wake-up resume signaling. This allows the upstream devices to get into their suspend state and prepare for propagating resume signaling. The FRESUM bit should be asserted to cause the resume state on the USB data lines for at least 10ms, but not more than 15ms. Note that the resume signalling is controlled by the FRESUM bit and meeting the timing specifications is dependent on the firmware. When FRESUM is cleared by firmware, the data lines will return to their high impedance state. Refer to Section 10.5.5 for more information about how the Force Resume (FRESUM) bit can be used to initiate the remote wake-up feature. 10.2.5 Low Speed Device
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Externally, low speed devices are configured by the position of a pull-up resistor on the USB D- pin of the MC68HC05JB4. Low speed devices are terminated as shown in Figure 10-10 with the pull-up on the D- line.
3.3V Regulator Out
68HC05JB4
1.5K D+ USB Low Speed Cable D-
Figure 10-10. External Low Speed Device Configuration For low speed transmissions, the transmitter's EOP width must be between 1.25s and 1.50s. These ranges include timing variations due to differential buffer delay and rise/fall time mismatches and to noise and other random effects. A low speed receiver must accept a 670ns wide SE0 followed by a J transition as a valid EOP. An SE0 narrower than 330ns or an SE0 not followed by a J transition must be rejected as an EOP. An EOP between 330ns and 670ns may be rejected or accepted as above. Any SE0 that is 2.5s or wider is automatically a reset. 10.3 CLOCK REQUIREMENTS The low speed data rate is nominally 1.5 Mbs. The OSCXCLK signal driven by the oscillator circuits is the clock source for the USB module and requires that a 6 MHz oscillator circuit be connected to the OSC1 and OSC2 pins. The permitted frequency tolerance for low speed functions is approximately 1.5% (15000 ppm). This tolerance includes inaccuracies from all sources: initial frequency accuracy, crystal capacitive loading, supply voltage on the oscillator, temperature, and aging. The jitter in the low speed data rate must be less than 10 ns. This tolerance allows the use of resonators in low cost, low speed devices. 10.4 HARDWARE DESCRIPTION The USB module as previously shown in Figure 10-1 contains four functional blocks: a 3.3 volt Regulator, a LS USB transceiver, the USB control logic, and the
MOTOROLA 10-10 UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
USB registers. The following will detail the function of the regulator, transceiver and control logic. See Section 10.5 for the register discussion. 10.4.1 Voltage Regulator The USB data lines are required by the USB Specification to have a maximum output voltage between 2.8V and 3.6V. The data lines are also required to have an external 1.5K pullup resistor connected between a data line and a voltage source between 3.0V and 3.6V. Since the power provided by the USB cable is specified to be between 4.4V and 5.0V, an on-chip regulator is used to drop the voltage to the appropriate level for sourcing the USB transceiver and external pullup resistor. An output pin driven by the regulator voltage is provided to source the 1.5K external resistor. Figure 10-11 shows the worst case electrical connection for the voltage regulator.
4.4V
Freescale Semiconductor, Inc...
3.3V Regulator R1 LS Transceiver
USB Data Lines
Host or Hub R2 R1 = 1.5K 5% R2 = 15K 5% R2
USB Cable
Figure 10-11. Regulator Electrical Connections 10.4.2 USB Transceiver The USB transceiver provides the physical interface to the USB D+ and D- data lines. The transceiver is composed of two parts: an output drive circuit and a differential receiver. 10.4.2.1 Output Driver Characteristics The USB transceiver uses a differential output driver to drive the USB data signal onto the USB cable. The static output swing of the driver in its low state is below the VOL of 0.3 V with a 1.5 k load to 3.6 V and in its high state is above the VOH of 2.8 V with a 15 k load to ground. The output swings between the differential high and low state are well balanced to minimize signal skew. Slew rate control on the driver is used to minimize the radiated noise and cross talk. The driver's outputs support three-state operation to achieve bi-directional half duplex operation. The driver can tolerate a voltage on the signal pins of -0.5 V to 3.8 V
MC68HC05JB4 REV 2 UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com MOTOROLA 10-11
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
with respect to local ground reference without damage. 10.4.2.2 Low Speed (1.5 Mbs) Driver Characteristics The rise and fall time of the signals on this cable are greater than 75 ns to keep RFI emissions under FCC class B limits, and less than 300 ns to limit timing delays and signaling skews and distortions. The driver reaches the specified static signal levels with smooth rise and fall times, and minimal reflections and ringing when driving the cable. This driver is used only on network segments between low speed devices and the ports to which they are connected.
ONE BIT TIME (1.5 Mb/s)
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VSE (max) VSE (min) VSS
SIGNAL PINS PASS OUTPUT SPEC LEVELS WITH MINIMAL REFLECTIONS AND RINGING
Figure 10-12. Low Speed Driver Signal Waveforms 10.4.3 Receiver Characteristics USB data transmission is done with differential signals. A differential input receiver is used to accept the USB data signal. A differential 1 on the bus is represented by D+ being at least 200 mV more positive than D- as seen at the receiver, and a differential 0 is represented by D- being at least 200 mV more positive than D+ as seen at the receiver. The signal cross over point must be between 1.3V and 2.0V. The receiver features an input sensitivity of 200 mV when both differential data inputs are in the range of 0.8 V to 2.5 V with respect to the local ground reference. This is called the common mode input voltage range. Proper data reception is also achieved when the differential data lines are outside the common mode range, as shown in Figure 10-13. The receiver can tolerate static input voltages between -0.5V to 3.8 V with respect to its local ground reference without damage. In addition to the differential receiver, there is a single-ended receiver (schmitt trigger) for each of the two data lines.
MOTOROLA 10-12
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
MINIMUM DIFFERENTIAL SENSITIVITY (VOLTS)
1.0
0.8
0.6
0.4
0.2
Freescale Semiconductor, Inc...
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
COMMON MODE INPUT VOLTAGE (VOLTS)
Figure 10-13. Differential Input Sensitivity Over Entire Common Mode Range 10.4.3.1 Receiver Data Jitter The data receivers for all types of devices must be able to properly decode the differential data in the presence of jitter. The more of the bit cell that any data edge can occupy and still be decoded, the more reliable the data transfer will be. Data receivers are required to decode differential data transitions that occur in a window plus and minus a nominal quarter bit cell from the nominal (centered) data edge position. Jitter will be caused by the delay mismatches and by mismatches in the source and destination data rates (frequencies). The receive data jitter budget for low speed is given in the electrical section of the this specification. The specification includes the consecutive (next) and paired transition values for each source of jitter. 10.4.3.2 Data Source Jitter The source of data can have some variation (jitter) in the timing of edges of the data transmitted. The time between any set of data transitions is N x TPERIOD jitter time, where `N' is the number of bits between the transitions and TPERIOD is defined as the actual period of the data rate. The data jitter is measured with the same capacitive load used for maximum rise and fall times and is measured at the crossover points of the data lines as shown in Figure 10-14.
MC68HC05JB4 REV 2
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MOTOROLA 10-13
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
tPeriod DIFFERENTIAL DATA LINES CROSSOVER POINTS
CONSECUTIVE TRANSITIONS PAIRED TRANSITIONS
Figure 10-14. Data Jitter
Freescale Semiconductor, Inc...
For low speed transmissions, the jitter time for any consecutive differential data transitions must be within 25 ns and within 10 ns for any set of paired differential data transitions. These jitter numbers include timing variations due to differential buffer delay, rise/fall time mismatches, internal clock source jitter, and to noise and other random effects. 10.4.3.3 Data Signal Rise and Fall Time The output rise time and fall time are measured between 10% and 90% of the signal. Edge transition time for the rising and falling edges of low speed signals is 75 ns (minimum) into a capacitive load (CL) of 50 pF and 300 ns (maximum) into a capacitive load of 350 pF. The rising and falling edges should be smooth transitional (monotonic) when driving the cable to avoid excessive EMI.
RISE TIME CL 90% DIFFERENTIAL DATA LINES 10% CL tR tF 10% FALL TIME 90%
LOW SPEED: 75 ns at CL = 50 pF, 300 ns at CL = 350 pF
Figure 10-15. Data Signal Rise and Fall Time 10.4.4 USB Control Logic The USB control logic manages data movement between the CPU and the transceiver. The control logic handles both transmit and receive operations on the USB. It contains the logic used to manipulate the transceiver and the endpoint registers. The logic contains byte count buffers for transmit operations that load the active transmit endpoints byte count and use this to determine the number of bytes to transfer. This same buffer is used for receive transactions to count the number of bytes received and, upon the end of the transaction, transfer that number to the receive endpoints byte count register.
MOTOROLA 10-14 UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
When transmitting, the control logic handles parallel to serial conversion, CRC generation, NRZI encoding, and bit stuffing. When Receiving, the control logic handles Sync detection, packet identification, end of packet detection, bit (un)stuffing, NRZI decoding, CRC validation, and serial to parallel conversion. Errors detected by the control logic include bad CRC, time-out while waiting for EOP, and bit stuffing violations. 10.4.4.1 Data Encoding/Decoding The USB employs NRZI data encoding when transmitting packets. In NRZI encoding, a 1 is represented by no change in level and a 0 is represented by a change in level. Figure 10-16 shows a data stream and the NRZI equivalent and Figure 10-17 is a flow diagram for NRZI. The high level represents the J state on the data lines in this and subsequent figures showing NRZI encoding. A string of zeros causes the NRZI data to toggle each bit time. A string of ones causes long periods with no transitions in the data.
0 DATA IDLE 1 1 0 1 0 1 0 0 0 1 0 0 1 1 0
Freescale Semiconductor, Inc...
NRZI
IDLE
Figure 10-16. NRZI Data Encoding
POWER UP NO PACKET TRANSMISSION IDLE BEGIN PACKET TRANSMISSION FETCH THE DATA BIT
NO
IS DATA BIT = 0?
YES
NO DATA TRANSITION
TRANSITION DATA
NO
IS PACKAGE TRANSFER DONE?
YES
Figure 10-17. Flow Diagram for NRZI
MC68HC05JB4 REV 2 UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com MOTOROLA 10-15
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
10.4.4.2 Bit Stuffing In order to ensure adequate signal transitions, bit stuffing is employed by the transmitting device when sending a packet on the USB (see Figure 10-18 and Figure 10-19). A 0 is inserted after every six consecutive 1's in the data stream before the data is NRZI encoded to force a transition in the NRZI data stream. This gives the receiver logic a data transition at least once every seven bit times to guarantee the data and clock lock. The receiver must decode the NRZI data, recognize the stuffed bits, and discard them. Bit stuffing is enabled beginning with the Sync Pattern and throughout the entire transmission. The data "one" that ends the Sync Pattern is counted as the first one in a sequence. Bit stuffing is always enforced, without exception. If required by the bit stuffing rules, a zero bit will be inserted even if it is the last bit before the end-of-packet (EOP) signal.
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RAW DATA
SYNC PATTERN
PACKET DATA STUFFED BIT
BIT STUFFED DATA NRZI ENCODED DATA
SYNC PATTERN SIX ONES
PACKET DATA
IDLE SYNC PATTERN PACKET DATA
Figure 10-18. Bit Stuffing
MOTOROLA 10-16
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
POWER UP NO PACKET TRANSMISSION IDLE BEGIN PACKET TRANSMISSION RESET BIT COUNTER TO 0
Freescale Semiconductor, Inc...
GET NEXT BIT
=0
BIT VALUE?
=1
INCREMENT THE COUNTER
NO
COUNTER = 6?
YES
INSERT A ZERO BIT
RESET THE BIT COUNTER TO 0
NO
IS PACKAGE TRANSFER DONE?
YES
Figure 10-19. Flow Diagram for Bit Stuffing 10.5 I/O REGISTER DESCRIPTION The USB Endpoint registers are comprised of a set of control/status registers and twenty-four data registers that provide storage for the buffering of data between the USB and the CPU. These registers are shown in Table 10-2. Table 10-2. Register Summary
MC68HC05JB4 REV 2
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MOTOROLA 10-17
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
Register Name USB Control Register 2 (UCR2)
Bit 7
6 0 TX1STR UADD6 RXD0F
5 TX1ST
4 0
3
2
1
Bit 0
Addr
ENABLE2 ENABLE1 STALL2 UADD3 TXD0IE UADD2 RXD0IE UADD1 0
STALL1 $0037 UADD0 $0038 0 $0039
USB Address Register USBEN (UADDR) USB Interrupt Register 0 (UIR0) USB Interrupt Register 1 (UIR1) TXD0F
UADD5 RSTF
UADD4 SUSPND 0 RESUMFR
TXD0FR RXD0FR 0 0
TXD1F
EOPF
RESUMF
TXD1IE
EOPIE
TXD1FR EOPFR
$003A
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USB Control Register 0 T0SEQ (UCR0) USB Control Register 1 T1SEQ (UCR1) USB Status Register (USR) RSEQ
STALL0 ENDADD SETUP
TX0E TX1E 0
RX0E
TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0 $003B
FRESUM TP1SIZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 $003C 0 RPSIZ3 RPSIZ2 RPSIZ1 RPSIZ0 $003D
USB Endpoint 0 Data UE0RD7 UE0RD6 UE0RD5 UE0RD4 Register 0 (UE0D0) UE0TD7 UE0TD6 UE0TD5 UE0TD4
UE0RD3 UE0RD2 UE0RD1 UE0RD0 UE0TD3 UE0TD2 UE0TD1 UE0TD0
$0020
USB Endpoint 0 Data UE0RD7 UE0RD6 UE0RD5 UE0RD4 Register 7 (UE0D7) UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 UE0TD3 UE0TD2 UE0TD1 UE0TD0
$0027
USB Endpoint 1/2 Data Register 0 (UE1D0) UE1TD7 UE1TD6 UE1TD5
UE1TD4
UE1TD3 UE1TD2 UE1TD1 UE1TD0
$0028
USB Endpoint 1/2 Data Register 7 (UE1D7) UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 = Unimplemented
$002F
10.5.1 USB Address Register (UADDR)
BIT 7 UADDR $0038 R W BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
USBEN
0
UADD6
0
UADD5
0
UADD4
0
UADD3
0
UADD2
0
UADD1
0
UADD0
0
reset:
Figure 10-20. USB Address Register (UADDR)
MOTOROLA 10-18
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
USBEN -- USB Module Enable This read/write bit enables and disables the USB module and the USB pins. When USBEN is clear, the USB module will not respond to any tokens. Reset clears this bit. 1 = USB function enabled 0 = USB function disabled UADD6-UADD0 -- USB Function Address These bits specify the USB address of the device. Reset clears these bits. 10.5.2 USB Interrupt Register 0 (UIR0)
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BIT 7 UIR0 $0039 R W 0 TXD0F
BIT 6 RXD0F 0
BIT 5 RSTF 0
BIT 4 SUSPND 0
BIT 3 TXD0IE 0
BIT 2 RXD0IE 0
BIT 1 0 TXD0FR 0
BIT 0 0 RXD0FR 0
reset:
= Unimplemented
Figure 10-21. USB Interrupt Register 0 (UIR0) TXD0F -- Endpoint 0 Data Transmit Flag This read only bit is set after the data stored in Endpoint 0 transmit buffers has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD0FR bit. To enable the next data packet transmission, TX0E must also be set. If TXD0F bit is not cleared, a NAK handshake will be returned in the next IN transaction. Reset clears this bit. Writing a logic 0 to TXD0F has no effect. 1 = Transmit on Endpoint 0 has occurred 0 = Transmit on Endpoint 0 has not occurred RXD0F -- Endpoint 0 Data Receive Flag This read only bit is set after the USB module has received a data packet and responded with an ACK handshake packet. Software must clear this flag by writing a logic 1 to the RXD0FR bit after all of the received data has been read. Software must also set RX0E bit to one to enable the next data packet reception. If RXD0F bit is not cleared, a NAK handshake will be returned in the next OUT transaction. Reset clears this bit. Writing a logic 0 to RXD0F has no effect. 1 = Receive on Endpoint 0 has occurred 0 = Receive on Endpoint 0 has not occurred RSTF -- USB Reset Flag This read only bit is set when a valid reset signal state is detected on the D+ and D- lines. This reset detection will also generate an internal reset signal to reset the CPU and other peripherals including the USB module. This bit is cleared by a POR reset.
MC68HC05JB4 REV 2 UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com MOTOROLA 10-19
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
SUSPND -- USB Suspend Flag To save power, this read/write bit should be set by the software if a 3ms constant idle state is detected on USB bus. Setting this bit stops the clock to the USB and causes the USB module to enter Suspend mode. Unnecessary analog circuitry will be powered down. Software must clear this bit after the Resume flag (RESUMF) is set while this Resume interrupt flag is serviced. TXD0IE -- Endpoint 0 Transmit Interrupt Enable This read/write bit enables the Transmit Endpoint 0 to generate a USB interrupt when the TXD0F bit becomes set. 1 = USB interrupts enabled for Transmit Endpoint 0 0 = USB interrupts disabled for Transmit Endpoint 0
Freescale Semiconductor, Inc...
RXD0IE -- Endpoint 0 Receive Interrupt Enable This read/write bit enables the Transmit Endpoint 0 to generate a USB interrupt when the RXD0F bit becomes set. 1 = USB interrupts enabled for Receive Endpoint 0 0 = USB interrupts disabled for Receive Endpoint 0 TXD0FR -- Endpoint 0 Transmit Flag Reset Writing a logic 1 to this write only bit will clear the TXD0F bit if it is set.Writing a logic 0 to TXD0FR has no effect. Reset clears this bit. RXD0FR -- Endpoint 0 Receive Flag Reset Writing a logic 1 to this write only bit will clear the RXD0F bit if it is set.Writing a logic 0 to RXD0FR has no effect. Reset clears this bit. 10.5.3 USB Interrupt Register 1 (UIR1)
BIT 7 UIR1 $003A R W 0 0 0 = Unimplemented TXD1F BIT 6 EOPF BIT 5 RESUMF BIT 4 0 RESUMFR 0 BIT 3 TXD1IE 0 BIT 2 EOPIE 0 BIT 1 0 TXD1FR 0 BIT 0 0 EOPFR 0
reset:
Figure 10-22. USB Interrupt Register 1(UIR1) TXD1F -- Endpoint 1/Endpoint 2 Data Transmit Flag This read only bit is shared by Endpoint 1 and Endpoint 2. It is set after the data stored in the shared Endpoint 1/Endpoint 2 transmit buffer has been sent and an ACK handshake packet from the host is received. Once the next set of data is ready in the transmit buffers, software must clear this flag by writing a logic 1 to the TXD1FR bit. To enable the next data packet transmission, TX1E must also be set. If TXD1F bit is not cleared, a NAK handshake will be returned in the next IN transaction. Reset clears this bit. Writing a logic 0 to TXD1F has no effect. 1 = Transmit on Endpoint 1 or Endpoint 2 has occurred 0 = Transmit on Endpoint 1 or Endpoint 2 has not occurred
MOTOROLA 10-20 UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
EOPF -- End of Packet Detect Flag This read only bit is set when a valid End-of-Packet sequence is detected on the D+ and D- lines. Software must clear this flag by writing a logic 1 to the EOPFR bit. Reset clears this bit. Writing a logic 0 to EOPF has no effect. 1 = End-of-Packet sequence has been detected 0 = End-of-Packet sequence has not been detected RESUMF -- Resume Flag This read only bit is set when USB bus activity is detected while the SUSPND bit is set. Software must clear this flag by writing a logic 1 to the RESUMFR bit. Reset clears this bit. Writing a logic 0 to RESUMF has no effect. 1 = USB bus activity has been detected 0 = No USB bus activity has been detected RESUMFR -- Resume Flag Reset Writing a logic 1 to this write only bit will clear the RESUMF bit if it is set. Writing a logic 0 to RESUMFR has no effect. Reset clears this bit. TXD1IE -- Endpoint 1/Endpoint 2 Transmit Interrupt Enable This read/write bit enables the USB to generate an interrupt when the shared Transmit Endpoint 1/Endpoint 2 interrupt flag (TXD1F) bit becomes set. Reset clears this bit. 1 = USB interrupts enabled for Transmit Endpoints 1 and 2 0 = USB interrupts disabled for Transmit Endpoints 1 and 2 EOPIE -- End of Packet Detect Interrupt Enable This read/write bit enables the USB to generate an interrupt when the EOPF bit becomes set. Reset clears this bit. 1 = USB interrupts enabled for Transmit Endpoints 1 and 2 0 = USB interrupts disabled for Transmit Endpoint 1 and 2 TXD1FR -- Endpoint 1/Endpoint 2 Transmit Flag Reset Writing a logic 1 to this write only bit will clear the TXD1F bit if it is set. Writing a logic 0 to TXD1FR has no effect. Reset clears this bit. EOPFR -- End of Packet Flag Reset Writing a logic 1 to this write only bit will clear the EOPF bit if it is set. Writing a logic 0 to the EOPFR has no effect. Reset clears this bit. 10.5.4 USB Control Register 0 (UCR0)
BIT 7 UCR0 $003B R W BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Freescale Semiconductor, Inc...
T0SEQ
0
STALL0
0
TX0E
0
RX0E
0
TP0SIZ3 TP0SIZ2 TP0SIZ1 TP0SIZ0
0 0 0 0
reset:
Figure 10-23. USB Control Register 0 (UCR0)
MC68HC05JB4 REV 2 UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com MOTOROLA 10-21
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
T0SEQ -- Endpoint 0 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction. Toggling of this bit must be controlled by software. Reset clears this bit. 1 = DATA1 Token active for next Endpoint 0 transmit 0 = DATA0 Token active for next Endpoint 0 transmit STALL0 -- Endpoint 0 Force Stall Bit This read/write bit causes Endpoint 0 to return a STALL handshake when polled by either an IN or OUT token by the USB Host Controller. The USB hardware clears this bit when a SETUP token is received. Reset clears this bit. 1 = Send STALL handshake 0 = Default TX0E -- Endpoint 0 Transmit Enable This read/write bit enables a transmit to occur when the USB Host controller sends an IN token to Endpoint 0. Software should set this bit when data is ready to be transmitted. It must be cleared by software when no more Endpoint 0 data needs to be transmitted. If this bit is 0 or the TXD0F is set, the USB will respond with a NAK handshake to any Endpoint 0 IN tokens. Reset clears this bit. 1 = Data is ready to be sent. 0 = Data is not ready. Respond with NAK. RX0E -- Endpoint 0 Receive Enable This read/write bit enables a receive to occur when the USB Host controller sends an OUT token to Endpoint 0. Software should set this bit when data is ready to be received. It must be cleared by software when data cannot be received. If this bit is 0 or the RXD0F is set, the USB will respond with a NAK handshake to any Endpoint 0 OUT tokens. Reset clears this bit. 1 = Data is ready to be received. 0 = Not ready for data. Respond with NAK. TP0SIZ3-TP0SIZ0 -- Endpoint 0 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for Endpoint 0. These bits are cleared by reset. 10.5.5 USB Control Register 1 (UCR1)
BIT 7 UCR1 $003C R W BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Freescale Semiconductor, Inc...
T1SEQ ENDADD
0 0
TX1E
0
FRESUM TP1SZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0
0 0 0 0 0
reset:
Figure 10-24. USB Control Register 1 (UCR1)
MOTOROLA 10-22
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
T1SEQ -- Endpoint1/Endpoint 2 Transmit Sequence Bit This read/write bit determines which type of data packet (DATA0 or DATA1) will be sent during the next IN transaction directed to Endpoint 1 or Endpoint 2. Toggling of this bit must be controlled by software. Reset clears this bit. 1 = DATA1 Token active for next Endpoint 1/Endpoint 2 transmit 0 = DATA0 Token active for next Endpoint 1/Endpoint 2 transmit ENDADD -- Endpoint Address Select This read/write bit specifies whether the data inside the registers UE1D0-UE1D7 are used for Endpoint 1 or Endpoint 2. If all the conditions for a successful Endpoint 2 USB response to a hosts IN token are satisfied (TXD1F=0, TX1E=1, STALL2=0, and ENABLE2=1) except that the ENDADD bit is configured for Endpoint 1, the USB responds with a NAK handshake packet. 1 = The data buffers are used for Endpoint 2 0 = The data buffers are used for Endpoint 1 TX1E -- Endpoint 1/Endpoint 2 Transmit Enable This read/write bit enables a transmit to occur when the USB Host controller sends an IN token to Endpoint 1 or Endpoint 2. The appropriate endpoint enable bit, ENABLE1 or ENABLE2 bit in the UCR2 register, should also be set. Software should set the TX1E bit when data is ready to be transmitted. It must be cleared by software when no more data needs to be transmitted. If this bit is 0 or the TXD1F is set, the USB will respond with a NAK handshake to any Endpoint 1 or Endpoint 2 directed IN tokens. Reset clears this bit. 1 = Data is ready to be sent. 0 = Data is not ready. Respond with NAK. FRESUM -- Force Resume This read/write bit forces a resume state ("K" or non-idle state) onto the USB data lines to initiate a remote wake-up. Software should control the timing of the forced resume to be between 10ms and 15 ms. Setting this bit will not cause the RESUMF bit to set. 1 = Force data lines to "K" state 0 = Default TP1SIZ3-TP1SIZ0 -- Endpoint 1/Endpoint 2 Transmit Data Packet Size These read/write bits store the number of transmit data bytes for the next IN token request for Endpoint 1 or Endpoint 2. These bits are cleared by reset. 10.5.6 USB Control Register 2 (UCR2)
BIT 7 UCR2 $0037 R W BIT 6 0 TX1STR 0 = Unimplemented BIT 5 TX1ST BIT 4 0 BIT 3 BIT 2 BIT 1 BIT 0
Freescale Semiconductor, Inc...
ENABLE2 ENABLE1 0 0
STALL2
0
STALL1
0
reset:
Figure 10-25. USB Control Register 2 (UCR2)
MC68HC05JB4 REV 2 UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com MOTOROLA 10-23
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
TX1STR -- Clear Transmit First Flag Writing a logic 1 to this write-only bit will clear the TX1ST bit if it is set. Writing a logic 0 to the TX1STR has no effect. Reset clears this bit. TX1ST -- Transmit First Flag This read-only bit is set if the Endpoint 0 Data Transmit Flag (TXD0F) is set when the USB control logic is setting the Endpoint 0 Data Receive Flag (RXD0F). That is, this bit will be set if an Endpoint 0 Transmit Flag is still set at the end of an Endpoint 0 reception. This bit lets the firmware know that the Endpoint 0 transmission happened before the Endpoint 0 reception. Reset clears this bit. 1 = IN transaction occurred before SETUP/OUT. 0 = IN transaction occurred after SETUP/OUT. ENABLE2 -- Endpoint 2 Enable This read/write bit enables Endpoint 2 and allows the USB to respond to IN packets addressed to Endpoint 2. Reset clears this bit. 1 = Endpoint 2 is enabled and can respond to an IN token. 0 = Endpoint 2 is disabled ENABLE1 -- Endpoint 1 Enable This read/write bit enables Endpoint 1 and allows the USB to respond to IN packets addressed to Endpoint 1. Reset clears this bit. 1 = Endpoint 1 is enabled and can respond to an IN token. 0 = Endpoint 1 is disabled STALL2 -- Endpoint 2 Force Stall Bit This read/write bit causes Endpoint 2 to return a STALL handshake when polled by either an IN or OUT token by the USB Host Controller. Reset clears this bit. 1 = Send STALL handshake. 0 = Default STALL1 -- Endpoint 1 Force Stall Bit This read/write bit causes Endpoint 1 to return a STALL handshake when polled by either an IN or OUT token by the USB Host Controller. Reset clears this bit. 1 = Send STALL handshake 0 = Default
Freescale Semiconductor, Inc...
MOTOROLA 10-24
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
10.5.7 USB Status Register (USR)
BIT 7 USR $003D R W U U U U = Unimplemented RSEQ BIT 6 SETUP BIT 5 0 BIT 4 0 BIT 3 RPSIZ3 U BIT 2 RPSIZ2 U BIT 1 BIT 0
RPSIZ1
U
RPSIZ0
U
reset:
Figure 10-26. USB Status Register (USR) RSEQ -- Endpoint 0 Receive Sequence Bit This read only bit indicates the type of data packet last received for Endpoint 0 (DATA0 or DATA1). 1 = DATA1 Token received in last Endpoint 0 receive 0 = DATA0 Token received in last Endpoint 0 receive SETUP -- SETUP Token Detect Bit This read only bit indicates that a valid SETUP token has been received. 1 = Last token received for Endpoint 0 was a SETUP token 0 = Last token received for Endpoint 0 was not a SETUP token RPSIZ3-RPSIZ0 -- Endpoint 0 Receive Data Packet Size These read only bits store the number of data bytes received for the last OUT or SETUP transaction for Endpoint 0. These bits are not affected by reset. 10.5.8 USB Endpoint 0 Data Registers (UE0D0-UE0D7)
BIT 7 UE0D0 $0020 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 : : : : : : : : : : : : : : : :
Freescale Semiconductor, Inc...
to
UE0D7 $0027
R UE0RD7 UE0RD6 UE0RD5 UE0RD4 UE0RD3 UE0RD2 UE0RD1 UE0RD0 W UE0TD7 UE0TD6 UE0TD5 UE0TD4 UE0TD3 UE0TD2 UE0TD1 UE0TD0 X X X X X X X X
reset:
Figure 10-27. USB Endpoint 0 Data Register (UE0D0-UE0D7) UE0RD7 - UE0RD0 -- Endpoint 0 Receive Data Buffer These read only bits are serially loaded with OUT token or SETUP token data received over the USB's D+ and D- pins. UE0TD7 - UE0TD0 -- Endpoint 0 Transmit Data Buffer These write only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at Endpoint 0.
MC68HC05JB4 REV 2
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MOTOROLA 10-25
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
10.5.9 USB Endpoint 1/Endpoint 2 Data Registers (UE1D0-UE1D7)
BIT 7 UE1D0 $0028 R W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 : : R W UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 X X X X X X X X : : : : : : : : : : : : : : BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
to
UE1D7 $002F
reset:
Figure 10-28. USB Endpoint 1/Endpoint2 Data Registers (UE1D0-UE1D7)
Freescale Semiconductor, Inc...
UE1TD7 - UE1TD0 -- Endpoint 1/ Endpoint 2 Transmit Data Buffer These write only buffers are loaded by software with data to be sent on the USB bus on the next IN token directed at Endpoint 1 or Endpoint 2. These buffers are shared by Endpoints 1 and 2 and depend on proper configuration of the ENDADD bit. 10.6 USB INTERRUPTS The USB module is capable of generating interrupts and causing the CPU to execute the USB interrupt service routine. There are three types of USB interrupts: * * * End of Transaction interrupts signify a completed transaction (receive or transmit) Resume interrupts signify that the USB bus is reactivated after having been suspended End of Packet interrupts signify that a low speed end of packet signal was detected
All USB interrupts share the same interrupt vector. Firmware is responsible for determining which interrupt is active. 10.6.1 USB End of Transaction Interrupt There are three possible end of transaction interrupts: Endpoint 0 Receive, Endpoint 0 Transmit, and a shared Endpoint 1 or Endpoint 2 Transmit. End of transaction interrupts occur as detailed in the following sections. 10.6.1.1 Receive Control Endpoint 0 For a Control OUT transaction directed at Endpoint 0, the USB module will generate an interrupt by setting the RXD0F flag in the UIR0 register. The conditions necessary for the interrupt to occur are shown in the flowchart of Figure 10-29. SETUP transactions cannot be stalled by the USB function. A SETUP received by a control endpoint will clear the STALL0 bit if it is set. The conditions for receiving
MOTOROLA 10-26 UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
a SETUP interrupt are shown in Figure 10-30. 10.6.1.2 Transmit Control Endpoint 0 For a Control IN transaction directed at Endpoint 0, the USB module will generate an interrupt by setting the TXD0F flag in the UIR0 register. The conditions necessary for the interrupt to occur are shown in the flowchart of Figure 10-31. 10.6.1.3 Transmit Endpoint 1 and Transmit Endpoint 2 Transmit Endpoints 1 & 2 share their interrupt flag. For an IN transaction directed at Endpoint 1 or 2, the USB module will generate an interrupt by setting the TXD1F flag in the UIR1 register. The conditions necessary for the interrupt to occur are shown in the flowchart of Figure 10-32. 10.6.2 Resume Interrupt The USB module will generate a USB interrupt if low speed bus activity is detected after entering the suspend state. A transition of the USB data lines to the non-idle state ("K" state) while in the suspend mode will set the RESUMF flag in the UIR1 register. There is no interrupt enable bit for this interrupt source and an interrupt will be executed if the I bit in the CCR is cleared. A resume interrupt can only occur while the MC68HC05JB4 is in the suspend mode. 10.6.3 End of Packet Interrupt The USB module can generate a USB interrupt upon detection of an end of packet signal (a single ended 0) for low speed devices. Upon detection of an SE0 sequence, the USB module sets the EOPF bit and will generate an interrupt if the EOPIE bit in the UIR1 register is set.
Freescale Semiconductor, Inc...
MC68HC05JB4 REV 2
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MOTOROLA 10-27
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
Valid OUT token received for Endpoint 0 Y Valid DATA token received for Endpoint 0? Y Endpoint 0 Receive Enabled? (USBEN = 1) Y N No Response from USB function N Time-out No Response from USB function
Freescale Semiconductor, Inc...
Endpoint 0 Receive Not Stalled? (STALL0 = 0) Y Endpoint 0 Receive Ready to Receive? (RX0E = 1) && (RXD0F = 0) Y
N
Send STALL Handshake
N
Send NAK Handshake
Accept Data Set/clear RSEQ bit
N Error free DATA packet? Y
Ignore transaction No response from USB function
Set RXD0F to 1
Receive Control Endpoint Interrupt Enabled? (RXD0IE = 1) Y Valid transaction Interrupt generated
N
No Interrupt
Figure 10-29. OUT Token Data Flow for Receive Endpoint 0
MOTOROLA 10-28
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
Valid SETUP token received for Endpoint 0 Y Endpoint 0 Receive Enabled? (USBEN = 1) Y Endpoint 0 Receive Ready to Receive? (RX0E = 1) && (RXD0F = 0) N No Response from USB function N No Response from USB function
Freescale Semiconductor, Inc...
Y STALL0 = 0? Y Accept Data set/clear RSEQ bit Set SETUP to 1 Y N Error free DATA packet? Y Set RXD0F to 1 Y Receive Control Endpoint Interrupt Enabled? (RXD0IE = 1) Y No Interrupt Valid transaction Interrupt generated N Ignore transaction No response from USB function N Clear STALL0 bit
Figure 10-30. SETUP Token Data Flow for Receive Endpoint 0
MC68HC05JB4 REV 2
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MOTOROLA 10-29
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
Valid IN token received for Endpoint 0 Y Transmit Endpoint Enabled? (USBEN = 1) Y Transmit Endpoint not Stalled by firmware? (STALL0 = 0) N Send STALL Handshake N No Response from USB function
Freescale Semiconductor, Inc...
Y Transmit Endpoint ready to Transfer? (TX0E = 1) && (TXD0F = 0) Y Send DATA Data PID set by T0SEQ N Send NAK Handshake
ACK received and no Time-out condition occur? Y
N
No Response from USB function
Set TXD0F to 1
Transmit Endpoint Interrupt Enabled? (TXD0IE = 1) Y Valid transaction Interrupt generated
N
No Interrupt
Figure 10-31. IN Token Data Flow for Transmit Endpoint 0
MOTOROLA 10-30
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
Valid IN token received for Endpoints 1 or 2 Y Transmit Endpoint Enabled? (USBEN = 1) Y Transmit Endpoint not Stalled by firmware? (STALL1 & ENDP1) + (STALL2 & ENDP2) Y N Send STALL Handshake N No Response from USB function
Freescale Semiconductor, Inc...
Transmit Endpoint ready to Transfer? (TX1E = 1) && (TXD1F = 0) & ((ENDP2 & ENDADD) + (ENDP1 & ENDADD)) Y Send DATA Data PID set by T1SEQ
N
Send NAK Handshake
ACK received and no Time-out condition occurs? Y
N
No Response from USB function
Set TXD1F to 1
Transmit Endpoint Interrupt Enabled? (TXD1IE = 1)
No Interrupt
Valid transaction Interrupt generated
Note: ENDP1 is Endpoint 1 directed traffic ENDP2 is Endpoint 2 directed traffic
Figure 10-32. IN Token Data Flow for Transmit Endpoint 1/2
MC68HC05JB4 REV 2
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MOTOROLA 10-31
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
Freescale Semiconductor, Inc...
MOTOROLA 10-32
UNIVERSAL SERIAL BUS MODULE For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
SECTION 11 ANALOG TO DIGITAL CONVERTER
The analog to digital converter system consists of a single 8-bit successive approximation converter and an 16-channel analog multiplexer. Six of the channels are available for analog inputs, four channels are dedicated to internal test functions, and the remaining six channels are unused. There is one 8-bit ADC Data Register ($0F) and one 8-bit ADC Status and Control register ($0E). The reference supply, VRL and VRH for the converter uses two input pins (shared with port pins PC4 and PC5) instead of the power supply lines, because drops caused by loading in the power supply lines would degrade the accuracy of the analog to digital conversion. An internal RC oscillator is available if the bus speed is low enough to degrade the ADC accuracy. An ADON bit allows the ADC to be switched off to reduce power consumption, which is particularly useful in the Wait mode.
Freescale Semiconductor, Inc...
Analog MUX (Channel assignment)
AD0 AD1 AD2 AD3 AD4 AD5
8-bit capacitive DAC with sample and hold
VRH VRL
Successive approximation register and control
Result 8 ADC Status and Control Register ($0E) CH0 CH1 CH2 CH3 ADON ADRC COCO
VRH
VRL (VRH +VRL)/4 (VRH +VRL)/2
ADC Data Register ($0F)
Figure 11-1. ADC Converter Block Diagram
MC68HC05JB4 REV 2
ANALOG TO DIGITAL CONVERTER For More Information On This Product, Go to: www.freescale.com
MOTOROLA 11-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
11.1
ADC OPERATION As shown in Figure 11-1, the ADC consists of an analog multiplexer, an 8-bit digital to analog capacitor array, a comparator and a successive approximation register (SAR). There are ten options that can be selected by the multiplexer; the AD0 to AD5 input pins, VRH, VRL, (VRH +VRL)/4, or (VRH +VRL)/2. Selection is done via the CHx bits in the ADC Status and Control Register. AD0 to AD5 are input points for ADC conversion operations; the others are reference points which can be used for test purposes. The converter uses VRH and VRL as reference voltages. An input voltage equal to or greater than VRH converts to $FF. An input voltage equal to or less than VRL, but greater than VSS, converts to $00. Maximum and minimum ratings must not be exceeded. Each analog input source should use VRH as the supply voltage and should be referenced to VRL for the ratiometric conversions. To maintain full accuracy of the ADC, the following should be noted: 1. VRH should be equal to or less than VCC; 2. VRL should be equal to or greater than VSS but less than maximum specifications; and 3. VRH-VRL should be equal to or greater than 4 Volts. The ADC reference inputs (VRH and VRL) are applied to a precision internal digital to analog converter. Control logic drives this D/A converter and the analog output is successively compared with the selected analog input sampled at the beginning of the conversion. The conversion is monotonic with no missing codes. The result of each successive comparison is stored in the successive approximation register (SAR) and, when the conversion is complete, the contents of the SAR are transferred to the read-only ADC Data Register ($0F), and the conversion complete flag, COCO, is set in the ADC Status and Control Register ($0E). NOTE Any write to the ADC Status and Control Register will abort the current conversion, reset the conversion complete flag (COCO) and a new conversion starts on the selected channel. At power-on or external reset, both the ADRC and ADON bits are cleared, thus the ADC is disabled.
Freescale Semiconductor, Inc...
MOTOROLA 11-2
ANALOG TO DIGITAL CONVERTER For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
11.2
ADC STATUS AND CONTROL REGISTER (ADSCR) The ADSCR is a read/write register containing status and control bits for the ADC.
BIT 7 ADSCR $000E reset: R W 0 COCO BIT 6 ADRC 0 BIT 5 ADON 0 BIT 4 0 0 BIT 3 CH3 0 BIT 2 CH2 0 BIT 1 CH1 0 BIT 0 CH0 0
Figure 11-2. A/D Status and Control Register COCO -- COnversion COmplete 1 = An ADC conversion has completed; ADC Data Register ($0F) contains valid conversion result. 0 = ADC conversion not completed. This read-only status bit is set when a conversion is completed, indicating that the ADC Data Register contains a valid result. This COCO bit is cleared either by a write to the ADSCR or a read of the ADC Data Register. Once the COCO bit is cleared, a new conversion automatically starts. If the COCO bit is not cleared, conversions are initiated every 32 cycles. In this continuous conversion mode the ADC Data Register is refreshed with new data, every 32 cycles, and the COCO bit remains set. ADRC -- ADC RC Oscillator Control 1 = ADC uses RC oscillator as clock source. 0 = ADC uses internal processor clock as clock source. The RC oscillator option must be used if the internal processor is running below 1MHz. A stabilization time of typically 1ms is required when switching to the RC oscillator option. ADON -- ADC On 1 = ADC is switched ON. 0 = ADC is switched OFF. When the ADC is turned from OFF to ON, it requires a time tADON for the current sources to stabilize. During this time ADC conversion results may be inaccurate. Switching the ADC off disables the internal charge pump and RC oscillator (if selected by ADRC=1), and hence saving power. CH3:CH0 -- Channel Select Bits These four bits selects one of ten ADC channels for the conversion. Channels 0 to 5 correspond to inputs AD0-AD5 on port pins PC0-PC3, PB3 and PB4 respectively. Channels 12 and 13 are the ADC reference inputs VRH and VRL, on port pins PC4 and PC5 respectively. Channels 14 and 15 are used for internal reference points. Table 11-1 shows the signals selected by the channel select bits.
Freescale Semiconductor, Inc...
MC68HC05JB4 REV 2
ANALOG TO DIGITAL CONVERTER For More Information On This Product, Go to: www.freescale.com
MOTOROLA 11-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
Table 11-1. A/D Channel Assignments
CH3
0 0 0 0 0 0
CH2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
CH1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
CH0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Channel
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Signal
AD0 (PC0) AD1 (PC1) AD2 (PC2) AD3 (PC3) AD4 (PB3) AD5 (PB4) Not Implemented Not Implemented Not Implemented Not Implemented Not Implemented Not Implemented VRH (PC4) VRL (PC5) (VRH+VRL)/4 (VRH+VRL)/2
Freescale Semiconductor, Inc...
0 0 1 1 1 1 1 1 1 1
Using a port pin as both an analog and digital input simultaneously is prohibited. When the ADC is enabled (ADON=1) and one of channels is selected, the corresponding port pin will appear as a logic zero when read from the Port Data Register. Note that the pull-up on a port-B pin will be disabled automatically when that port pin is selected as the ADC input and the ADON bit is set to logic "1". 11.3 ADC DATA REGISTER (ADDR) The ADDR stores the result of a valid ADC conversion when the COCO bits is set in ADSCR.
BIT 7 ADDR $000F reset: R W ADDR7 0 BIT 6 ADDR6 0 BIT 5 ADDR5 0 BIT 4 ADDR4 0 BIT 3 ADDR3 0 BIT 2 ADDR2 0 BIT 1 ADDR1 0 BIT 0 ADDR0 0
Figure 11-3. A/D Data Register
MOTOROLA 11-4
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MC68HC05JB4 REV 2
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11.4
ADC DURING LOW POWER MODES The ADC continues normal operation in WAIT mode. To reduce power consumption in WAIT mode, the ADON and ADRC bits in the ADSCR should be cleared if the ADC is not used. If the ADC is in use and the internal bus clock is above 1MHz, it is recommended that the ADRC bit be cleared. In STOP mode, the ADC stops operation.
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MC68HC05JB4 REV 2
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MOTOROLA 11-5
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MOTOROLA 11-6
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SECTION 12 INSTRUCTION SET
This section describes the addressing modes and instruction types. 12.1 ADDRESSING MODES The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes define the manner in which the CPU finds the data required to execute an instruction. The eight addressing modes are the following: * * * * * * * * Inherent Immediate Direct Extended Indexed, No Offset Indexed, 8-Bit Offset Indexed, 16-Bit Offset Relative
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12.1.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no memory address and are one byte long. 12.1.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no memory address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte.
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MOTOROLA 12-1
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12.1.3 Direct Direct instructions can access any of the first 256 memory addresses with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. BRSET and BRCLR are three-byte instructions that use direct addressing to access the operand and relative addressing to specify a branch destination. 12.1.4 Extended
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Extended instructions use only three bytes to access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. 12.1.5 Indexed, No Offset Indexed instructions with no offset are one-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the conditional address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location. 12.1.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are two-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the conditional address of the operand. These instructions can access locations $0000-$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode.
MOTOROLA 12-2
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12.1.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions are three-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the conditional address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. These instructions can address any location in memory. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory.
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As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. 12.1.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the conditional branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement byte that gives a branching range of -128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 12.1.9 Instruction Types The MCU instructions fall into the following five categories: * * * * * Register/Memory Instructions Read-Modify-Write Instructions Jump/Branch Instructions Bit Manipulation Instructions Control Instructions
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MOTOROLA 12-3
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12.1.10 Register/Memory Instructions Most of these instructions use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 12-1 lists the register/memory instructions.
Table 12-1. Register/Memory Instructions
Instruction
Add Memory Byte and Carry Bit to Accumulator
Mnemonic
ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB
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Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator
MOTOROLA 12-4
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12.1.11 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. The test for negative or zero instruction (TST) is an exception to the read-modify-write sequence because it does not write a replacement value. Table 12-2 lists the read-modify-write instructions. Table 12-2. Read-Modify-Write Instructions
Instruction Mnemonic
ASL ASR BCLR BSET CLR COM DEC INC LSL LSR NEG ROL ROR TST
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Arithmetic Shift Left Arithmetic Shift Right Clear Bit in Memory Set Bit in Memory Clear Complement (One's Complement) Decrement Increment Logical Shift Left Logical Shift Right Negate (Two's Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero
12.1.12 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump to subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. All branch instructions use relative addressing. Bit test and branch instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These three-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the conditional branch destination by adding the
MC68HC05JB4 REV 2 INSTRUCTION SET For More Information On This Product, Go to: www.freescale.com MOTOROLA 12-5
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. Table 12-3 lists the jump and branch instructions. Table 12-3. Jump and Branch Instructions
Instruction
Branch if Carry Bit Clear Branch if Carry Bit Set
Mnemonic
BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL BRA BRCLR BRN BRSET BSR JMP JSR
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Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine
MOTOROLA 12-6
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12.1.13 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory. Port registers, port data direction registers, timer registers, and on-chip RAM locations are in the first 256 bytes of memory. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Bit manipulation instructions use direct addressing. Table 12-4 lists these instructions. Table 12-4. Bit Manipulation Instructions
Instruction Mnemonic
BCLR BRCLR BRSET BSET
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Clear Bit Branch if Bit Clear Branch if Bit Set Set Bit
12.1.14 Control Instructions These register reference instructions control CPU operation during program execution. Control instructions, listed in Table 12-5, use inherent addressing. Table 12-5. Control Instructions
Instruction
Clear Carry Bit Clear Interrupt Mask No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts
Mnemonic
CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT
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MOTOROLA 12-7
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12.1.15 Instruction Set Summary Table 12-6 is an alphabetical list of all M68HC05 instructions and shows the effect of each instruction on the condition code register. Table 12-6. Instruction Set Summary
Opcode Source Form
ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel
Operation
Description
HINZC
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Add with Carry
A (A) + (M) + (C)
--
IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX
A9 ii B9 dd C9 hh ll D9 ee ff E9 ff F9 AB ii BB dd CB hh ll DB ee ff EB ff FB A4 ii B4 dd C4 hh ll D4 ee ff E4 ff F4 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 dd
Add without Carry
A (A) + (M)
--
Logical AND
A (A) (M)
----
--
Arithmetic Shift Left (Same as LSL)
C b7 b0
0
----

ff dd
Arithmetic Shift Right
b7 b0
C
----
DIR INH INH IX1 IX REL
ff
Branch if Carry Bit Clear
PC (PC) + 2 + rel ? C = 0
----------
rr dd dd dd dd dd dd dd dd rr rr rr
BCLR n opr
Clear Bit n
Mn 0
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- ---------- REL REL REL
BCS rel BEQ rel BHCC rel
Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear
PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1 PC (PC) + 2 + rel ? H = 0
MOTOROLA 12-8
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MC68HC05JB4 REV 2
Cycles
2 3 4 5 4 3 2 3 4 5 4 3 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3
Effect on CCR
Operand
Address Mode
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Table 12-6. Instruction Set Summary (Continued)
Opcode Source Form
BHCS rel BHI rel BHS rel BIH rel
Operation
Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low
Description
PC (PC) + 2 + rel ? H = 1
HINZC
----------
REL REL REL REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) REL
29 22 24 2F 2E
rr rr rr rr rr
PC (PC) + 2 + rel ? C Z = 0 -- -- -- -- -- PC (PC) + 2 + rel ? C = 0 PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 ---------- ---------- ----------
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BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel
Bit Test Accumulator with Memory Byte
(A) (M)
----
--
A5 ii B5 dd C5 hh ll D5 ee ff E5 ff F5 p 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 00 02 04 06 08 0A 0C 0E 21 rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr
Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always
PC (PC) + 2 + rel ? C = 1
----------
PC (PC) + 2 + rel ? C Z = 1 -- -- -- -- -- PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1 ---------- ---------- ---------- ---------- ---------- ----------
BRCLR n opr rel Branch if bit n clear
PC (PC) + 2 + rel ? Mn = 0
--------
BRSET n opr rel Branch if Bit n Set
PC (PC) + 2 + rel ? Mn = 1
--------
BRN rel
Branch Never
PC (PC) + 2 + rel ? 1 = 0
----------
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MOTOROLA 12-9
Cycles
3 3 3 3 3 2 3 4 5 4 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 3
Effect on CCR
Operand
Address Mode
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Table 12-6. Instruction Set Summary (Continued)
Opcode Source Form Operation Description Cycles
5 5 5 5 5 5 5 5 6 2 2 dd 5 3 3 6 5 2 3 4 5 4 3 5 3 3 6 5 2 3 4 5 4 3 5 3 3 6 5 2 3 4 5 4 3
Effect on CCR HINZC
BSET n opr
Set Bit n
Mn 1
DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7)
10 12 14 16 18 1A 1C 1E
dd dd dd dd dd dd dd dd
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BSR rel
Branch to Subroutine Clear Carry Bit Clear Interrupt Mask
PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel C0 I0 M $00 A $00 X $00 M $00 M $00
----------
REL
AD
CLC CLI CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X
-------- 0 -- 0 ------
INH INH DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX
98 9A 3F 4F 5F 6F 7F
Clear Byte
---- 0 1 --
Compare Accumulator with Memory Byte
(A) - (M)
----
A1 ii B1 dd C1 hh ll D1 ee ff E1 ff F1 33 43 53 63 73 dd
Complement Byte (One's Complement)
M (M) = $FF - (M) A (A) = $FF - (M) X (X) = $FF - (M) M (M) = $FF - (M) M (M) = $FF - (M)
----
1
Compare Index Register with Memory Byte
(X) - (M)
----
A3 ii B3 dd C3 hh ll D3 ee ff E3 ff F3 3A 4A 5A 6A 7A dd
Decrement Byte
M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1
----
--
EXCLUSIVE OR Accumulator with Memory Byte
A (A) (M)
----
--
A8 ii B8 dd C8 hh ll D8 ee ff E8 ff F8
MOTOROLA 12-10
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MC68HC05JB4 REV 2
Operand
rr ff ff ff
Address Mode
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Table 12-6. Instruction Set Summary (Continued)
Opcode Source Form
INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP
Operation
Description
M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1
HINZC
Increment Byte
----
--
DIR INH INH IX1 IX DIR EXT IX2 IX1 IX DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH
3C 4C 5C 6C 7C
dd
ff
Unconditional Jump
PC Jump Address
----------
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BC dd CC hh ll DC ee ff EC ff FC BD dd CD hh ll DD ee ff ED ff FD A6 ii B6 dd C6 hh ll D6 ee ff E6 ff F6 AE ii BE dd CE hh ll DE ee ff EE ff FE 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D ii dd
Jump to Subroutine
PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Conditional Address
----------
Load Accumulator with Memory Byte
A (M)
----
--
Load Index Register with Memory Byte
X (M)
----
--
Logical Shift Left (Same as ASL)
C b7 b0
0
----
ff dd
Logical Shift Right
0 b7 b0
C
---- 0
ff
Unsigned Multiply
X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M)
0 ------ 0
11 5 3 3 6 5 2
Negate Byte (Two's Complement)
----
ff
No Operation
----------
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MOTOROLA 12-11
Cycles
5 3 3 6 5 2 3 4 3 2 5 6 7 6 5 2 3 4 5 4 3 2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5
Effect on CCR
Operand
Address Mode
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Table 12-6. Instruction Set Summary (Continued)
Opcode Source Form
ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X ROR opr RORA RORX ROR opr,X ROR ,X RSP
Operation
Description
HINZC
Logical OR Accumulator with Memory
A (A) (M)
----
--
IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH
AA ii BA dd CA hh ll DA ee ff EA ff FA 39 49 59 69 79 36 46 56 66 76 9C dd
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Rotate Byte Left through Carry Bit
C b7 b0
----
ff dd
Rotate Byte Right through Carry Bit
C b7 b0
----
ff
Reset Stack Pointer
SP $00FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL)
----------
RTI
Return from Interrupt

INH
80
RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X
Return from Subroutine
----------
INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX
81 A2 ii B2 dd C2 hh ll D2 ee ff E2 ff F2 99 9B B7 dd C7 hh ll D7 ee ff E7 ff F7 8E BF dd CF hh ll DF ee ff EF ff FF
Subtract Memory Byte and Carry Bit from Accumulator
A (A) - (M) - (C)
----
Set Carry Bit Set Interrupt Mask
C1 I1
-------- 1 -- 1 ------
Store Accumulator in Memory
M (A)
----
--
Stop Oscillator and Enable IRQ Pin
-- 0 ------
Store Index Register In Memory
M (X)
----
--
MOTOROLA 12-12
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MC68HC05JB4 REV 2
Cycles
2 3 4 5 4 3 5 3 3 6 5 5 3 3 6 5 2 9 6 2 3 4 5 4 3 2 2 4 5 6 5 4 2 4 5 6 5 4
Effect on CCR
Operand
Address Mode
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Table 12-6. Instruction Set Summary (Continued)
Opcode Source Form
SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X
Operation
Description
HINZC
Subtract Memory Byte from Accumulator
A (A) - (M)
----
IMM DIR EXT IX2 IX1 IX
A0 ii B0 dd C0 hh ll D0 ee ff E0 ff F0
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SWI
Software Interrupt
PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) -- 1 ------ SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte X (A) ----------
INH
83
10
TAX TST opr TSTA TSTX TST opr,X TST ,X TXA
Transfer Accumulator to Index Register
INH DIR INH INH IX1 IX INH
97 3D 4D 5D 6D 7D 9F dd
Test Memory Byte for Negative or Zero
(M) - $00
----
--
ff
Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts
A (X)
----------
WAIT
A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n
-- 0 ------
opr PC PCH PCL REL rel rr SP X Z # () -( ) ? : --
INH
8F
Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit
Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected
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MOTOROLA 12-13
Cycles
2 3 4 5 4 3 2 4 3 3 5 4 2 2
Effect on CCR
Operand
Address Mode
0 1 2 3 4 5 6 7 8 9 A B C D E F
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MOTOROLA 12-14
MSB LSB
Table 12-7. Opcode Map
Bit Manipulation Branch DIR 0
5
Read-Modify-Write DIR 3 INH 4
5 3
Control IX 7
6 5
Register/Memory IMM A
2
DIR 1
5
REL 2
3
INH 5
3
IX1 6
NEG
IX1 1
INH 8
9
INH 9
DIR B
3
EXT C
4
IX2 D
5
IX1 E
4
IX F
3
MSB LSB
BRSET0
DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2 5 DIR 2
BSET0
DIR 2 5
BRA
REL 2 3
NEG
DIR 1
NEGA
INH 1
NEGX
INH 2
NEG
IX 1
RTI
INH 6 2
SUB
IMM 2 2
SUB
DIR 3 3
SUB
EXT 3 4
SUB
IX2 2 5
SUB
IX1 1 4
SUB
IX 3
3
0 1 2 3 4 5 6 7 8 9 A B C D E F
BRCLR0 BRSET1
BCLR0
DIR 2 5
BRN
REL 3 1 11
RTS
INH 2
CMP
IMM 2 2
CMP
DIR 3 3
CMP
EXT 3 4
CMP
IX2 2 5
CMP
IX1 1 4
CMP
IX 3
3
BSET1
DIR 2 5
BHI
REL 3 1 5
MUL
INH 3 2 3 6 5 10
SBC
IMM 2 2
SBC
DIR 3 3
SBC
EXT 3 4
SBC
IX2 2 5
SBC
IX1 1 4
SBC
IX 3
3
BRCLR1 BRSET2
BCLR1
DIR 2 5
BLS
REL 2 3
COM
DIR 1 5
COMA
INH 1 3
COMX
INH 2 3
COM
IX1 1 6
COM
IX 1 5
SWI
INH 2
CPX
IMM 2 2
CPX
DIR 3 3
CPX
EXT 3 4
CPX
IX2 2 5
CPX
IX1 1 4
CPX
IX 3
3
BSET2
DIR 2 5
BCC
REL 2 3 REL 3
LSR
DIR 1
LSRA
INH 1
LSRX
INH 2
LSR
IX1 1
LSR
IX 2
AND
IMM 2 2
AND
DIR 3 3
AND
EXT 3 4
AND
IX2 2 5
AND
IX1 1 4
AND
IX 3
3
INSTRUCTION SET MC68HC05JB4 REV 2
BRCLR2 BRSET3
BCLR2 BSET3
BCS/BLO
2 5 3 3 6 5
BIT
IMM 2 2
BIT
DIR 3 3
BIT
EXT 3 4
BIT
IX2 2 5
BIT
IX1 1 4
BIT
IX 3
3
DIR 2 5 DIR 2 5
BNE
REL 2 3
ROR
DIR 1 5
RORA
INH 1 3
RORX
INH 2 3
ROR
IX1 1 6
ROR
IX 5 2 2
LDA
IMM 2
LDA
DIR 3 4
LDA
EXT 3 5
LDA
IX2 2 6
LDA
IX1 1 5
LDA
IX 4
3
BRCLR3 BRSET4
BCLR3
DIR 2 5
BEQ
REL 2 3
ASR
DIR 1 5 DIR 1 5
ASRA
INH 1 3 INH 1 3
ASRX
INH 2 3 INH 2 3
ASR
IX1 1 6 IX1 1 6
ASR
IX 5 IX 5 1
TAX
INH 2 2 2
STA
DIR 3 3
STA
EXT 3 4
STA
IX2 2 5
STA
IX1 1 4
STA
IX 3
3
BSET4
DIR 2 5
BHCC BHCS
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ROL
DIR 1 5
ASL/LSL
1
CLC
INH 2 2
EOR
IMM 2 2
EOR
DIR 3 3
EOR
EXT 3 4
EOR
IX2 2 5
EOR
IX1 1 4
EOR
IX 3
3
REL 2 3 REL 2 3
BRCLR4 BRSET5
BCLR4
DIR 2 5
ROLA
INH 1 3
ROLX
INH 2 3
ROL
IX1 1 6
ROL
IX 5 1
SEC
INH 2 2
ADC
IMM 2 2
ADC
DIR 3 3
ADC
EXT 3 4
ADC
IX2 2 5
ADC
IX1 1 4
ADC
IX 3
3
BSET5
DIR 2 5
BPL
REL 2 3
DEC
DIR 1
DECA
INH 1
DECX
INH 2
DEC
IX1 1
DEC
IX 1
CLI
INH 2 2
ORA
IMM 2 2
ORA
DIR 3 3
ORA
EXT 3 4
ORA
IX2 2 5
ORA
IX1 1 4
ORA
IX 3
3
BRCLR5 BRSET6
BCLR5
DIR 2 5
BMI
REL 3 1 5 3 3 6 5
SEI
INH 2 2
ADD
IMM 2
ADD
DIR 3 2
ADD
EXT 3 3
ADD
IX2 2 4
ADD
IX1 1 3
ADD
IX 2
3
BSET6
DIR 2 5
BMC
REL 2 3
INC
DIR 1 4
INCA
INH 1 3
INCX
INH 2 3
INC
IX1 1 5
INC
IX 4 1
RSP
INH 2 2 6
JMP
DIR 3 5
JMP
EXT 3 6
JMP
IX2 2 7
JMP
IX1 1 6
JMP
IX 5
3
BRCLR6 BRSET7
BCLR6
DIR 2 5
BMS
REL 2 3
TST
DIR 1
TSTA
INH 1
TSTX
INH 2
TST
IX1 1
TST
IX 2 1
NOP
INH 2
BSR
REL 2 2
JSR
DIR 3 3
JSR
EXT 3 4
JSR
IX2 2 5
JSR
IX1 1 4
JSR
IX 3
3
BSET7
DIR 2 5
BIL
REL 3 1 5 3 3 6 5
STOP
INH 2 2 2
LDX
IMM 2
LDX
DIR 3 4
LDX
EXT 3 5
LDX
IX2 2 6
LDX
IX1 1 5
LDX
IX 4
3
BRCLR7
3
BCLR7
DIR 2
BIH
REL 2
CLR
DIR 1
CLRA
INH 1
CLRX
INH 2
CLR
IX1 1
CLR
IX 1
WAIT
INH 1
TXA
INH 2
STX
DIR 3
STX
EXT 3
STX
IX2 2
STX
IX1 1
STX
IX
INH = Inherent IMM = Immediate DIR = Direct EXT = Extended
REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset
MSB LSB LSB of Opcode in Hexadecimal 0
3
0
MSB of Opcode in Hexadecimal
5 Number of Cycles
BRSET0 Opcode Mnemonic
DIR Number of Bytes/Addressing Mode
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
SECTION 13 ELECTRICAL SPECIFICATIONS
This section describes the electrical and timing specifications of the MC68HC05JB4. 13.1 MAXIMUM RATINGS
Freescale Semiconductor, Inc...
(Voltages referenced to VSS)
Rating
Supply Voltage Current Drain Per Pin Excluding VDD and VSS Input Voltage IRQ/VPP Pin Storage Temperature Range
Symbol
VDD I VIN VPP TSTG
Value
-0.3 to +7.0 25 VSS - 0.3 to VSS + 0.3 VSS -0.3 to 17 -65 to +150
Unit
V mA V V C
NOTE Maximum ratings are the extreme limits the device can be exposed to without causing permanent damage to the chip. The device is not intended to operate at these conditions. The MCU contains circuitry that protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIN and VOUT within the range from VSS (VIN or VOUT) VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD. 13.2 THERMAL CHARACTERISTICS
Characteristic
Thermal Resistance 28-pin PDIP 28-pin SOIC
Symbol
JA JA
Value
60 60
Unit
C/W C/W
MC68HC05JB4 REV 2
ELECTRICAL SPECIFICATIONS For More Information On This Product, Go to: www.freescale.com
MOTOROLA 13-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
13.3
DC ELECTRICAL CHARACTERISTICS Table 13-1. DC Electrical Characteristics
(VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0C to +70C, unless otherwise noted)
Characteristic Output Voltage ILoad = 10.0 A Output High Voltage (ILoad =-0.8 mA) PA0-7, PB0-4, PC0-5 Output Low Voltage (ILoad = 1.6 mA) PA0-4, PB0-4, PC0-5 (ILoad = 10.0 mA) PA5-7 (ILoad = 25.0 mA) PA6, PA7 (mask option) Input High Voltage PA0-7, PB0-4, PC0-5, IRQ, RESET, OSC1 Input Low Voltage PA0-7, PB0-4, PC0-5, IRQ, RESET, OSC1 Supply Current (see Notes) Run (USB active) Run (USB suspended) Wait (USB active) Wait (USB suspended) Stop
LVR off at 25C (not inlcude 15k to GND)
Symbol VOL VOH VOH
Min -- VDD-0.1 VDD-0.8 -- -- -- 0.7xVDD VSS -- -- -- -- --
Typ -- -- -- -- -- -- -- -- 4.0 3.5 1.5 1.0 130
Max 0.1 -- -- 0.4 0.4 0.5 VDD 0.2xVDD 4.5 4.0 2.0 1.5 180
Unit V
V
Freescale Semiconductor, Inc...
VOL
V
VIH VIL
V V mA mA mA mA A A A pF pF
IDD
I/O Ports Hi-Z Leakage Current PA0-7, PB0-4, PC0-5 (without individual pulldown/up activated) Input Current RESET, IRQ, OSC1 Capacitance Ports (as Input or Output) RESET, IRQ, OSC1, OSC2 Crystal/Ceramic Resonator Oscillator Mode Internal Resistor OSC1 to OSC2 Pullup Resistor PA0-7, PB0-4 LVR Inhibit LVR Recover
IZ
--
--
10 5 12 8
Iin Cout Cin
-- -- --
-- -- --
ROSC RPULLUP VLVRI VLVRR
1.0 30 -- --
2.0 50 3.3 3.5
3.0 75 -- --
M K V V
MOTOROLA 13-2
ELECTRICAL SPECIFICATIONS For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
NOTES: 1. 2. 3. 4. 5. 6. 7.
All values shown reflect average measurements. Typical values at midpoint of voltage range, 25C only. Wait IDD: Only MFT and Timer1 active. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 (fOSC = 6.0 MHz), all inputs 0.2 VDC from rail; no DC loads, less than 50pF on all outputs, CL = 20 pF on OSC2. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 VDC, VIH = VDD-0.2 VDC. Stop IDD measured with OSC1 = VSS. Wait IDD is affected linearly by the OSC2 capacitance.
13.4
USB DC ELECTRICAL CHARACTERISTICS Table 13-2. USB DC Electrical Characteristics
Freescale Semiconductor, Inc...
(VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0C to +70C, unless otherwise noted)
Characteristic Hi-Z State Data Line Leakage Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold Static Output Low Static Output High 3.3V External Reference Pin
Symbol ILO VDI VCM VSE VOL VOH V3.3
Conditions 0VMin -10 0.2 0.8 0.8
Typ
Max +10
Unit A V
2.5 2.0 0.3
V V V V V
RL of 1.5k to 3.6V RL of 15k to GND IL=200A 2.8 3.0 3.3
3.6 3.6
MC68HC05JB4 REV 2
ELECTRICAL SPECIFICATIONS For More Information On This Product, Go to: www.freescale.com
MOTOROLA 13-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
13.5
USB LOW SPEED SOURCE ELECTRICAL CHARACTERISTICS Table 13-3. USB Low Speed Source Electrical Characteristics
Parameter Symbol Conditions (Notes 1,2,3) Notes 4, 5, 8 CL=50pF CL=350pF CL=50pF CL=350pF TR/TF Min Typ Max Unit
Transition time: Rise Time Fall Time Rise/Fall Time Matching
TR TF TRFM VCRS TDRATE
75 75 80 1.3
-- -- -- -- 1.500 666.0 -- -- -- -- -- --
-- 300 -- 300 120 2.0 1.5225 656.8 25 10 75 45 1.50 100
ns ns ns ns % V Mbs ns ns ns ns ns s ns
Freescale Semiconductor, Inc...
Output Signal Crossover Voltage Low Speed Data Rate Source Differential Driver Jitter To Next Transition For Paired Transitions Receiver Data Jitter Tolerance To Next Transition For Paired Transitions Source EOP Width Differential to EOP Transition Skew Receiver EOP Width Must Reject as EOP Must Accept
NOTES: 1. 2. 3. 4. 5. 6. 7. 8.
1.5Mbs 1.5% CL=350pF Notes 6 and 7 CL=350pF Notes 7 Note 7 Note 7
1.4775 676.8 -25 -10 -75 -45 1.25 -40
TUDJ1 TUDJ2 TDJR1 TDJR2 TEOPT TDEOP
TEOPR1 TEOPR2
Note 7
330 675
-- --
-- --
ns ns
All voltages measured from local ground, unless otherwise specified. All timings use a capacitive load of 50pF, unless otherwise specified. Low speed timings have a 1.5k pull-up to 2.8V on the D- data line. Measured from 10% to 90% of the data signal. The rising and falling edges should be smooth transitions (monotonic). Timing differences between the differential data signals. Measured at crossover point of differential data signals. Capacitive loading includes 50pF of tester capacitance.
MOTOROLA 13-4
ELECTRICAL SPECIFICATIONS For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
13.6
CONTROL TIMING Table 13-4. Control Timing
(VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0C to +70C, unless otherwise noted)
Characteristic Frequency of Operation Crystal Oscillator Option External Clock Source Internal Operating Frequency Crystal Oscillator (fOSC / 2) External Clock (fOSC / 2)
Symbol fOSC fOSC fOP fOP tCYC tRL tILIH tILIL tIHIL tIHIH tOH, tOL tSLOW
Min -- DC -- DC 330 1.5 0.5 note 1 0.5 note 1 --
Max 6 6 3 3 -- -- -- --
--
Units MHz MHz MHz MHz ns tCYC tCYC tCYC tCYC tCYC ns tCYC
Freescale Semiconductor, Inc...
Cycle Time (1/fOP) RESET Pulse Width Low IRQ Interrupt Pulse Width Low (Edge-Triggered) IRQ Interrupt Pulse Period PA0 to PA3 Interrupt Pulse Width High (Edge-Triggered) PA0 to PA3 Interrupt Pulse Period OSC1 Pulse Width Output High to Low Transition Period on PA6, PA7, PB0-4
-- --
0.5 (typical)
NOTES: 1. The minimum period tILIL or tIHIH should not be less than the number of cycles it takes to execute the interrupt service routine plus 19 tCYC.
MC68HC05JB4 REV 2
ELECTRICAL SPECIFICATIONS For More Information On This Product, Go to: www.freescale.com
MOTOROLA 13-5
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
Freescale Semiconductor, Inc...
MOTOROLA 13-6
ELECTRICAL SPECIFICATIONS For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
SECTION 14 MECHANICAL SPECIFICATIONS
This section provides the mechanical dimensions for the 28-pin PDIP and 28-pin SOIC packages. 14.1 28-PIN PDIP (CASE 710)
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040
Freescale Semiconductor, Inc...
28
15
B
1 14
A N
C
L
H
G
F D
K
SEATING PLANE
M
J
14.2
28
28-PIN SOIC (CASE 751F)
-A15 14X NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 17.80 18.05 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 BSC 0.23 0.32 0.13 0.29 0 8 10.01 10.55 0.25 0.75 INCHES MIN MAX 0.701 0.711 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 0 8 0.395 0.415 0.010 0.029
-B1 14
P 0.010 (0.25)
M
B
M
28X
D
M
0.010 (0.25)
TA
S
B
S
M R C
X 45
26X
G K
-TSEATING PLANE
F J
MC68HC05JB4 REV 2
MECHANICAL SPECIFICATIONS For More Information On This Product, Go to: www.freescale.com
MOTOROLA 14-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
Freescale Semiconductor, Inc...
MOTOROLA 14-2
MECHANICAL SPECIFICATIONS For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
APPENDIX A MC68HC705JB4
This appendix describes the MC68HC705JB4, the emulation part for MC68HC05JB4. The entire MC68HC05JB4 data sheet applies to the MC68HC705JB4, with exceptions outlined in this appendix.
Freescale Semiconductor, Inc...
A.1
INTRODUCTION The MC68HC705JB4 is an EPROM version of the MC68HC05JB4, and is available for user system evaluation and debugging. The MC68HC705JB4 is functionally identical to the MC68HC05JB4 with the exception of the 3584 bytes user ROM is replaced by 3584 bytes user EPROM. Also, the mask options available on the MC68HC05JB4 are implemented using the Mask Option Register (MOR) in the MC68HC705JB4.
A.2
MEMORY The MC68HC705JB4 memory map is shown in Figure A-1.
A.3
MASK OPTION REGISTER (MOR) The Mask Option Register (MOR) is a byte of EPROM used to select the features controlled by mask options on the MC68HC05JB4. In order to program this register the MORON bit in PCR need to be set to "1" before doing the EPROM programming process.
BIT 7 MOR $007F reset: R W 0 0 BIT 6 BIT 5 COPEN 1 BIT 4 IRQTRIG 1 BIT 3
HIGHCURRA
BIT 2
BIT 1
BIT 0 LVREN 1
PAINTEN OSCDLY 1 1
1
COPEN - COP Enable 1 = COP watchdog function disabled. 0 = COP watchdog function enabled. IRQTRIG - IRQ, PA0-PA3 Interrupt Options 1 = Edge-trigger only. 0 = Edge-and-level-triggered. HIGHCURRA - PA6 and PA7 High Current Enable 1 = High current capability disabled on PA6 and PA7. 0 = High current capability enabled on PA6 and PA7.
MC68HC05JB4 REV 2 For More Information On This Product, Go to: www.freescale.com
MOTOROLA A-1
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
PAINTEN - PA0-PA3 External Interrupt Options 1 = External interrupt capability on PA0-PA3 disabled. 0 = External interrupt capability on PA0-PA3 enabled. OSCDLY - Oscillator Delay Option 1 = 128 internal clock cycles. 0 = 4064 internal clock cycles. LVREN - LVR Option 1 = Low Voltage Reset circuit enabled. 0 = Low Voltage Reset circuit disabled.
Freescale Semiconductor, Inc...
$0000 I/O Registers 64 Bytes $003F $0040 $007E $007F $0080 I/O Registers Unused 63 Bytes Mask Option Register User RAM 176 Bytes $00C0 64 Byte Stack $00FF $012F $0130 Unused 3792 Bytes $0FFF $1000 User EPROM 3584 Bytes $1DFF $1E00 $1FEF $1FF0 $1FFF 64 Bytes EPROM Program Control Register
$0000
$003E $003F $1FF0 $1FF1 $1FF2 $1FF3 $1FF4 $1FF5 $1FF6 $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF
Reserved Reserved Reserved Reserved
MFT Vector (High Byte) MFT Vector (Low Byte) Timer1 Vector (High Byte) Timer1 Vector (Low Byte) USB Vector (High Byte) USB Vector (Low Byte) IRQ/IRQ2 Vector (High Byte) IRQ/IRQ2 Vector (Low Byte)
Bootstrap ROM 496 Bytes User Vectors 16 Bytes
SWI Vector (High Byte) SWI Vector (Low Byte) Reset Vector (High Byte) Reset Vector (Low Byte)
Figure A-1. MC68HC705JB4 Memory Map A.4 BOOTSTRAP MODE Bootloader mode is entered upon the rising edge of RESET if the IRQ/VPP pin is at VTST and the PB0 pin is at logic zero. The Bootloader program is masked in the ROM area from $1E00 to $1FEF. This program handles copying of user code from an external EPROM into the on-chip EPROM. The bootload function has to be done from an external EPROM. The bootloader performs one programming pass at 1ms per byte then does a verify pass.
MOTOROLA A-2 For More Information On This Product, Go to: www.freescale.com MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
The user code must be a one-to-one correspondence with the internal EPROM addresses. A.5 EPROM PROGRAMMING Programming the on-chip EPROM is achieved by using the Program Control Register located at address $3E. Please contact Motorola for programming board availability. A.5.1 EPROM Program Control Register (PCR) This register is provided for programming the on-chip EPROM in the MC68HC705JB4.
Freescale Semiconductor, Inc...
BIT 7 PCR $003E reset: R W 0
BIT 6
BIT 5 RESERVED
BIT 4
BIT 3
BIT 2 MORON
BIT 1 ELAT 0
BIT 0 PGM 0
0
0
0
0
0
MORON - Mask Option Register ON 0 = Disable programming to Mask Option Register ($007F) 1 = Enable programming to Mask Option Register ($007F) ELAT - EPROM LATch control 0 = EPROM address and data bus configured for normal reads 1 = EPROM address and data bus configured for programming (writes to EPROM cause address and data to be latched). EPROM is in programming mode and cannot be read if ELAT is 1. This bit should not be set when no programming voltage is applied to the Vpp pin. PGM - EPROM ProGraM command 0 = Programming power is switched OFF from EPROM array. 1 = Programming power is switched ON to EPROM array. If ELAT 1, then PGM = 0. A.5.2 Programming Sequence The EPROM programming sequence is: 1. Set the ELAT bit 2. Write the data to the address to be programmed 3. Set the PGM bit 4. Delay for a time tPGMR 5. Clear the PGM bit 6. Clear the ELAT bit The last two steps must be performed with separate CPU writes.
MC68HC05JB4 REV 2 For More Information On This Product, Go to: www.freescale.com MOTOROLA A-3
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
CAUTION It is important to remember that an external programming voltage must be applied to the VPP pin while programming, but it should be equal to VDD during normal operations. Figure A-2 shows the flow required to successfully program the EPROM.
START
Freescale Semiconductor, Inc...
ELAT=1
Write EPROM byte
EPGM=1
Wait 1ms
EPGM=0
ELAT=0
Y
Write additional byte? N END
Figure A-2. EPROM Programming Sequence
MOTOROLA A-4 For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
February 24, 1999 GENERAL RELEASE SPECIFICATION
A.6
EPROM PROGRAMMING SPECIFICATIONS Table A-1. EPROM Programming Electrical Characteristics
(VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0C to +40C, unless otherwise noted) Characteristic Programming Voltage
IRQ/VPP VPP IPP tEPGM
Symbol
Min -- -- --
Typ 13.5 5
1
Max -- 10 --
Unit V mA ms
Programming Current
IRQ/VPP
Programming Time
Freescale Semiconductor, Inc...
per byte
A.7
DC ELECTRICAL CHARACTERISTICS Table A-2. DC Electrical Characteristics (705JB4)
(VDD = 4.2V to 5.5V, VSS = 0 Vdc, TA = 0C to +40C, unless otherwise noted)
Characteristic Supply Current (see Notes) Run (USB active) Run (USB suspended) Wait (USB active) Wait (USB suspended) Stop LVR off at 25C (not include 15k to GND)
Symbol
Min -- -- -- -- --
Typ -- -- -- -- 130
Max 7.5 6.5 4.0 3.0 180
Unit mA mA mA mA A
IDD
MC68HC05JB4 REV 2 For More Information On This Product, Go to: www.freescale.com
MOTOROLA A-5
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION February 24, 1999
Freescale Semiconductor, Inc...
MOTOROLA A-6 For More Information On This Product, Go to: www.freescale.com
MC68HC05JB4 REV 2
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
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